Resettable Encoded Vector Clock for Causality Analysis With an Application to Dynamic Race Detection

• Published in: IEEE transactions on parallel and distributed systems Vol. 32; no. 4; pp. 772 - 785
• Main Authors: Pozzetti, Tommaso, Kshemkalyani, Ajay D.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.04.2021; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Causality; clock reset protocol; Clocks; Clocks & watches; dynamic race detection; Encoding; Message passing; Message systems; Performance enhancement; Prime numbers; Protocols; Scalability; vector clock
• ISSN: 1045-9219; 1558-2183; 2161-9883; 1558-2183
• DOI: 10.1109/TPDS.2020.3032293

Causality tracking among events is a fundamental challenge in distributed environments. Much previous work on this subject has focused on designing an efficient and scalable protocol to represent logical time. Several implementations of logical clocks have been proposed, most recently the Encoded Vector Clock (EVC), a protocol to encode Vector Clocks (VC) in scalar numbers through the use of prime numbers, to improve performance and scalability. We propose and formalize the concept of Resettable Encoded Vector Clock (REVC), a new logical clock implementation, which builds on the EVC to tackle its very high growth rate issue. We show how our REVC can be applied in both shared memory systems and message passing systems to achieve a consistent logical clock. We show, through practical examples, the advantage of REVC's growth rate with respect to EVC's growth rate. Finally, we show a practical application of the REVC to the dynamic race detection problem in multi-threaded environments. We compare our tool to the currently existing VC-based tool <inline-formula><tex-math notation="LaTeX">\text{DJIT}^+</tex-math> <mml:math><mml:msup><mml:mtext>DJIT</mml:mtext><mml:mo>+</mml:mo></mml:msup></mml:math><inline-graphic xlink:href="kshemkalyani-ieq1-3032293.gif"/> </inline-formula> to show how the REVC can help in achieving higher performance with respect to the Vector Clock.