Exploiting loop-level parallelism on coarse-grained reconfigurable architectures using modulo scheduling

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Bibliographic Details
Published inIEE proceedings. Computers and digital techniques Vol. 150; no. 5; pp. 255 - 261
Main Authors Mei, B., Vernalde, S., Verkest, D., De Man, H., Lauwereins, R.
Format Journal Article Conference Proceeding
LanguageEnglish
Published Stevenage Institution of Electrical Engineers 01.09.2003
Subjects
Applied sciences
Computers, microcomputers
Design. Technologies. Operation analysis. Testing
Electronics
Exact sciences and technology
Hardware
Input-output equipment
Integrated circuits
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Performance evaluation
Compiler
VLSI circuit
Circuit design
Codesign
Three dimensional space
Scheduling
Parallel architectures
Modeling
Circuit architecture
Boarded computer
Experimental result
Algorithm performance
Coarse grain structure
Electronic design automation
Test method
Reconfigurable architectures
Abstract space
Resource management
Computer aided design
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ISSN1350-2387
DOI10.1049/ip-cdt:20030833

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ISSN:1350-2387
DOI:10.1049/ip-cdt:20030833