Design of a pipelined radix 4 CORDIC processor

• Published in: Parallel computing Vol. 19; no. 7; pp. 729 - 744
• Main Authors: Bruguera, J.D, Antelo, E, Zapata, E.L
• Format: Journal Article
• Language: English
• Published: Amsterdam Elsevier B.V 01.07.1993; Elsevier
• Subjects: Applied sciences; CORDIC algorithm; Digital signal processing; Distributed computer systems; Electronics; Exact sciences and technology; Hardware; pipelining; redundant arithmetic; signed-digit adders; CORDIC algorithm; pipelining; signed-digit adders; Digital signal processing; redundant arithmetic; Parallelism; Pipeline; Digital signal
• ISSN: 0167-8191; 1872-7336
• DOI: 10.1016/0167-8191(93)90061-O

In this work we develop a generalization of the CORDIC algorithm for any radix in three coordinate systems, linear, circular and hyperbolic. We carry out a comparative study between different radixes at the number of additions level, due to the fact that the complexity in additions determines the total hardware associated with the implementation of the algorithm. Radix 4 minimizes the number of additions, therefore we propose a high speed CORDIC processor based on this radix 4. We have developed new criteria for the vectorization and rotation modes and we introduce a new technique for the compensation of a non-constant scale factor, multifactor compensation. The processor we propose is of a general and pipelined character and uses reductant arithmetic (signed digit) in order to reduce the delay in each stage, parallelizing the operation of the adders using a competitive implementation (reduction of the number of stages) with respect to radix 2 implementations which have recently appeared in the literature.