A Design of Autonomous Error-Tolerant Architectures for Massively Parallel Computing

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 26; no. 10; pp. 2143 - 2154
• Main Authors: Liu, Lizheng, Jin, Yi, Liu, Yi, Ma, Ning, Huan, Yuxiang, Zou, Zhuo, Zheng, Lirong
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.10.2018; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Circuit faults; Computation; Computer architecture; Embedded systems; Error analysis; Error detection; Error tolerant; Maintenance; Microprocessors; nanosystem; Parallel processing; Power consumption; Processors; Program processors; Redundancy; self-reparation; sensing; Sensors
• ISSN: 1063-8210; 1557-9999; 1557-9999
• DOI: 10.1109/TVLSI.2018.2846298

The massively parallel computing systems composed of many processors are connected on chips, which will become more and more complex and unreliable. This paper presents an error-tolerant design based on the autonomous error-tolerant (AET) architecture that aims to have a self-repairing capability. A nearby error sensing mechanism is designed to discover faults, and an active evolution scheme is studied to handle unrecoverable errors. A circuit backup switching mechanism is proposed to bypass the failed nodes. The board-level prototype is implemented based on dual-core embedded processors. The analysis shows that the error-tolerant capability of the proposed architecture is better than the conventional multimodular redundant system when the failure rate of a single core is less than 0.7. In the AET test system consisting of 16 processors, the error-tolerant capability is verified. The results show that the relative variation of the overall performance of the AET system will not be changed due to the high reliability requirements of the system. Through experimental comparison, under the premise that the architecture of AET and the triple modular redundancy method are basically consistent in reliability, whether on the logical-level error tolerant or on the physical-level error tolerant, the former has lower power consumption.