High-Bandwidth Chiplet Interconnects for Advanced Packaging Technologies in AI/ML Applications: Challenges and Solutions

• Published in: IEEE open journal of solid-state circuits Vol. 4; pp. 351 - 364
• Main Authors: Li, Shenggao, Lin, Mu-Shan, Chen, Wei-Chih, Tsai, Chien-Chun
• Format: Journal Article
• Language: English
• Published: IEEE 2024
• Subjects: 3D-IC; 3Dblox; advanced packaging; Artificial intelligence; artificial intelligence (AI) and compute; Bandwidth; chiplet integration; Chiplets; Energy efficiency; Integrated circuit interconnections; Interconnected systems; interconnects; Packaging; Signal integrity; Silicon; Thermal stresses; Three-dimensional displays; Universal Chiplets Interconnect Express (UCIe)
• ISSN: 2644-1349; 2644-1349
• DOI: 10.1109/OJSSCS.2024.3506694

The demand for chiplet integration using 2.5D and 3D advanced packaging technologies has surged, driven by the exponential growth in computing performance required by artificial intelligence and machine learning (AI/ML). This article reviews these advanced packaging technologies and emphasizes critical design considerations for high-bandwidth chiplet interconnects, which are vital for efficient integration. We address challenges related to bandwidth density, energy efficiency, electromigration, power integrity, and signal integrity. To avoid power overhead, the chiplet interconnect architecture is designed to be as simple as possible, employing a parallel data bus with forwarded clocks. However, achieving highyield manufacturing and robust performance still necessitates significant efforts in design and technology co-optimization. Despite these challenges, the semiconductor industry is poised for continued growth and innovation, driven by the possibilities unlocked by a robust chiplet ecosystem and novel 3D-IC design methodologies.