Novel Field-Programmable Gate Array Architecture for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 22; no. 3; pp. 522 - 536
• Main Authors: Kasap, Server, Redif, Soydan
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.03.2014; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; Architecture (computers); Computation; Computer architecture; Coordinate rotation digital computer (CORDIC); Decomposition; Field programmable gate arrays; field-programmable gate array (FPGA); Hardware; Jacobian matrices; Mathematical models; Matrix decomposition; Polynomial matrices; polynomial matrix eigenvalue decomposition; Polynomials; Random access memory; sequential best rotation (SBR2); Xilinx system generator tool
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2013.2248069

In this paper, we introduce a field-programmable gate array (FPGA) hardware architecture for the realization of an algorithm for computing the eigenvalue decomposition (EVD) of para-Hermitian polynomial matrices. Specifically, we develop a parallelized version of the second-order sequential best rotation (SBR2) algorithm for polynomial matrix EVD (PEVD). The proposed algorithm is an extension of the parallel Jacobi method to para-Hermitian polynomial matrices, and as such, it is the first architecture devoted to PEVD. Hardware implementation of the algorithm is achieved via a highly pipelined, nonsystolic FPGA architecture. The efficient hardware solution is accomplished by using the coordinate rotation digital computer algorithm to calculate the trigonometric functions and vector multiplications that are performed by the algorithm. The architecture, which is scalable in terms of the size of the input para-Hermitian matrix, has been designed using the Xilinx system generator tool. We verify the algorithmic convergence of the architecture and demonstrate its decomposition performance through computer simulations and FPGA-in-the-loop hardware co-simulations. Results confirm that the proposed solution gives low execution times while reducing the number of resources required from the FPGA.