Fault Tolerant Network on Chip Switching With Graceful Performance Degradation

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems Vol. 29; no. 6; pp. 883 - 896
• Main Authors: Kohler, Adan, Schley, Gert, Radetzki, Martin
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.06.2010; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Adaptive routing; Algorithms; Chips; Communication switching; Computer networks; Degradation; Delay; Fault diagnosis; Fault tolerance; Faults; graceful degradation; Multiprocessor interconnection networks; network fault tolerance; network on chip; Network-on-a-chip; Networks; online fault diagnosis; Redundancy; Routing; Switches; Switching theory
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/TCAD.2010.2048399

The structural redundancy inherent to on-chip interconnection networks [networks on chip (NoC)] can be exploited by adaptive routing algorithms in order to provide connectivity even if network components are out of service due to faults, which will appear at an increasing rate with future chip technology nodes. This paper is based on a new, fine-grained functional fault model and a corresponding distributed fault diagnosis method that facilitate determining the fault status of individual NoC switches and their adjacent communication links. Whereas previous work on network fault-tolerance assume switches to be either available or fully out of service, we present a novel adaptive routing algorithm that employs the remaining functionality of partly defective switches. Using diagnostic information, transient faults are handled with a retransmission scheme that avoids the latency penalty of end-to-end repeat requests. Thereby, graceful degradation of NoC communication performance can be achieved even under high failure rates.