SimPL: An Effective Placement Algorithm

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems Vol. 31; no. 1; pp. 50 - 60
• Main Authors: Myung-Chul Kim, Dong-Jin Lee, Markov, I. L.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.01.2012; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithm design and analysis; Algorithms; Benchmark testing; Benchmarking; Computer aided design; Convergence; Design engineering; Integrated circuit interconnections; Integrated circuits; layout; Mathematical models; multicore; Optimization; Parallel processing; Partitioning algorithms; physical design; Placement; Running
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/TCAD.2011.2170567

We propose a self-contained, flat, quadratic global placer that is simpler than existing placers and easier to integrate into timing-closure flows. It maintains lower-bound and upper-bound placements that converge to a final solution. The upper-bound placement is produced by a novel look-ahead legalization algorithm. Our placer SimPL outperforms mPL6, FastPlace3, NTUPlace3, APlace2, and Capo simultaneously in runtime and solution quality, running 7.10 times faster than mPL6 (when using a single thread) and reducing wirelength by 3% on the ISPD 2005 benchmark suite. More significant improvements are achieved on larger benchmarks. The new algorithm is amenable to parallelism, and we report empirical studies with SSE2 instructions and up to eight parallel threads.