DCD - The Multi-Channel Current-Mode ADC Chip for the Readout of DEPFET Pixel Detectors

The current-mode ADC chip-prototype for the readout of DEPFET particle pixel-detectors with high spatial resolution is presented. The planned application of these DEPFET detectors are vertex detectors for ILC and Belle II. The chip has 72 ADC channels. Every channel processes the input signals using...

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Bibliographic Details
Published inIEEE transactions on nuclear science Vol. 57; no. 2; pp. 743 - 753
Main Authors Peric, Ivan, Armbruster, Tim, Koch, Manuel, Kreidl, Christian, Fischer, Peter
Format Journal Article
LanguageEnglish
Published New York IEEE 01.04.2010
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects
Belle II
Channels
Chips
Circuits
CMOS
CMOS technology
Conversion
current copier
current-mode A/D converter
current-mode memory cell
cyclic (algorithmic) A/D converter
DEPFET detector
Detectors
Error correction
ILC
Noise measurement
Power consumption
Semiconductor device measurement
Signal processing
Signal resolution
Signal to noise ratio
Spatial resolution
switched-current memory cell
Time measurement
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ISSN0018-9499
1558-1578
DOI10.1109/TNS.2010.2040487

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Summary:The current-mode ADC chip-prototype for the readout of DEPFET particle pixel-detectors with high spatial resolution is presented. The planned application of these DEPFET detectors are vertex detectors for ILC and Belle II. The chip has 72 ADC channels. Every channel processes the input signals using two cyclic ADCs that operate in parallel. The cyclic ADCs are based on current-mode memory cells. The measured signal to noise ratio of one ADC is about 660 (fast ADC variant: 520) and its conversion time is 320 ns (fast ADC variant: 160 ns) in the case of 8-bit resolution. Redundant signed-digit cyclic conversion is used for automated digital error correction. One ADC-core occupies only 40 ¿m × 55 ¿m, its static power consumption is 0.96 mW. Besides the two ADCs, every channel contains a regulated cascode and two additional current-mode memory cells that allow double-sampling of the input signal. Due to the need for high radiation tolerance, the chip has been implemented in a 180 nm CMOS technology using enclosed NMOS gate layouts. Novel radiation-hard circuits have been used. The chip has also been used to read out a small DEPFET test matrix.
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ISSN:0018-9499
1558-1578
DOI:10.1109/TNS.2010.2040487