Power-Efficient RAM Mapping Algorithms for FPGA Embedded Memory Blocks

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems Vol. 26; no. 2; pp. 278 - 290
• Main Authors: Tessier, R., Betz, V., Neto, D., Egier, A., Gopalsamy, T.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.02.2007; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; Computer simulation; Design; Design automation; Design engineering; Dynamics; Field programmable gate arrays; field-programmable gate arrays (FPGAs); Hardware; Heuristic algorithms; Logic; Mapping; memory architecture; power demand; Power dissipation; Power measurement; Random access memory; Read-write memory; Size control; Testing
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/TCAD.2006.887924

Contemporary field-programmable gate array (FPGA) design requires a spectrum of available physical resources. As FPGA logic capacity has grown, locally accessed FPGA embedded memory blocks have increased in importance. When targeting FPGAs, application designers often specify high-level memory functions, which exhibit a range of sizes and control structures. These logical memories must be mapped to FPGA embedded memory resources such that physical design objectives are met. In this paper, a set of power-efficient logical-to-physical RAM mapping algorithms is described, which converts user-defined memory specifications to on-chip FPGA memory block resources. These algorithms minimize RAM dynamic power by evaluating a range of possible embedded memory block mappings and selecting the most power-efficient choice. Our automated approach has been validated with both simulation of power dissipation and measurements of power dissipation on FPGA hardware. A comparison of measured power reductions to values determined via simulation confirms the accuracy of our simulation approach. Our power-aware RAM mapping algorithms have been integrated into a commercial FPGA compiler and tested with 34 large FPGA benchmarks. Through experimentation, we show that, on average, embedded memory dynamic power can be reduced by 26% and overall core dynamic power can be reduced by 6% with a minimal loss (1%) in design performance. In addition, it is shown that the availability of multiple embedded memory block sizes in an FPGA reduces embedded memory dynamic power by an additional 9.6% by giving more choices to the computer-aided design algorithms