A 17 GHz direct digital synthesizer in a InP DHBT technology

• Published in: Sadhana (Bangalore) Vol. 46; no. 3
• Main Authors: Zhang, Yi, Li, Xiaopeng, Zhang, Youtao, Zhang, Min, Guo, Yufeng, Gao, Hao
• Format: Journal Article
• Language: English
• Published: New Delhi Springer India 01.09.2021; Springer Nature B.V
• Subjects: Algorithms; Digital to analog conversion; Digital to analog converters; Engineering; Figure of merit; Heterojunction bipolar transistors; Phased arrays; Power consumption; Radar arrays; Radar equipment; Semiconductor devices; Synthesis; nonlinear DAC; DDS; InP DHBT; phase accumulator; clock distribution
• ISSN: 0256-2499; 0973-7677
• DOI: 10.1007/s12046-021-01710-4

Direct digital synthesizer (DDS) is an essential part of the multi-band digital phased array radar system due to its broad frequency generation ability. In this paper, a 17 GHz 8-bit ROM-less DDS in a 0.7 μm InP double hetero-junction bipolar transistor (DHBT) technology is presented. The DDS adopts a sin-weighted nonlinear Digital-to-Analog Converter (DAC) to achieve phase-to-amplitude conversion. A simplified pipelined phase accumulator is applied, and its adder is designed according to the majority decision algorithm to reduce power consumption. The DDS is fabricated in an in-house 0.7 μm InP DHBT technology. The measured results demonstrate that the maximum input clock frequency is 17 GHz, and it can synthesize sin-wave outputs from 66.41 MHz to 8.5 GHz in 66.41 MHz steps. The average Spurious-free dynamic range (SFDR) for the output signal of the DDS is − 18.1 dBc. The chip integrates about 1700 transistors, consumes 7.4 W, and has a Figure of merit (FOM) of 2.3 GHz/W.