A New Angle Set-Based Absolute Scaling-free Reconfigurable Cordic Algorithm

• Published in: Circuits, systems, and signal processing Vol. 42; no. 12; pp. 7404 - 7432
• Main Authors: Changela, Ankur, Zaveri, Mazad, Kumar, Yogesh
• Format: Journal Article
• Language: English
• Published: New York Springer US 01.12.2023; Springer Nature B.V
• Subjects: Algorithms; Approximation; Circuits and Systems; Convergence; Digital computers; Electrical Engineering; Electronics and Microelectronics; Engineering; Field programmable gate arrays; Hyperbolic trajectories; Instrumentation; Mathematical analysis; Reconfiguration; Rotation; Scaling; Signal,Image and Speech Processing; Taylor series; Effective word length; Scaling-free angle set; FPGA Implementation; Absolute scaling-free CORDIC; Reconfigurable CORDIC architecture
• ISSN: 0278-081X; 1531-5878
• DOI: 10.1007/s00034-023-02452-w

This article presents a reconfigurable rotation mode coordinate rotation digital computer (CORDIC) algorithm that can be configured in hyperbolic or circular trajectories. The proposed CORDIC algorithm employs the new angle set to acquire the absolute scaling-free rotation in circular or hyperbolic trajectories. The proposed new angle set is represented using only power of two terms, which helps to compute the rotation using only shift and add architecture. The effective word length is taken as a measure to check the accuracy of the proposed angle set. The original scaling-free CORDIC algorithm has a limited range of convergence from - π 4 to π 4 . The proposed algorithm achieves the convergence range from - π 2 to π 2 through a new proposed angle set. In the proposed angle set, the power of the two terms used to represent the hyperbolic and circular rotations are similar, resulting in an architecture with a minimum reconfiguration resource. The first four stages rotate the rotating vector through the proposed angle set to bring down the rotation angle to a minimum value, which enables the use of the Taylor approximation for successive stages without any error. The last two stages use the first-order Taylor series approximation to realize the scaling-free rotation. The fully pipelined architecture is described using Verilog HDL and synthesized to map on Virtex-5 field-programmable gate arrays using the Xilinx Vivado design suite. The synthesis results suggest that the proposed CORDIC architecture uses 23.03% and 19.36% fewer resources as compared to architectures (Aggarwal and Meher, in: 2014 IEEE International Symposium on Circuits and Systems (ISCAS), 2014) and (Aggarwal et al. in IEEE Trans Very Large Scale Integr. (VLSI) Syst 24(4):1588–1592, 2016), respectively.