Optimal port allocation scheme for deflection-routed networks-on-chip

• Published in: The Journal of supercomputing Vol. 77; no. 12; pp. 14161 - 14179
• Main Authors: Stojanovic, Igor, Jovanovic, Milica, Djosic, Sandra, Djordjevic, Goran Lj
• Format: Journal Article
• Language: English
• Published: New York Springer US 01.12.2021; Springer Nature B.V
• Subjects: Compilers; Computer Science; Deflection; Hardware; Interpreters; Permutations; Processor Architectures; Programming Languages; Routers; System on chip; Bufferless router; Port allocation; Network-on-chip; Deflection routing
• ISSN: 0920-8542; 1573-0484
• DOI: 10.1007/s11227-021-03850-0

Deflection routing is considered a promising approach for improving the energy efficiency of networks-on-chip (NoCs) because of its hardware simplicity and minimal buffer requirements. The major weakness of the deflection routing is poor performance under high network load because of excessive flit deflections that occur in routers as a result of resolving frequent port conflicts. In this paper, we propose a design solution for optimal port allocation in permutation-network-based deflection NoC routers. The proposed solution requires 3.3× fewer hardware resources compared to a naïve implementation of the optimal port allocation scheme while providing 38.6% higher network throughput than a commonly used suboptimal port allocation scheme. We also present a novel low-cost suboptimal port allocator, which improves the network throughput by 17.4% over the conventional port allocator with comparable hardware complexity.