Optimized Gate Diffusion Input Method-Based Reversible Magnitude Arithmetic Unit Using Non-dominated Sorting Genetic Algorithm II

• Published in: Circuits, systems, and signal processing Vol. 39; no. 9; pp. 4516 - 4551
• Main Authors: Abiri, Ebrahim, Darabi, Abdolreza, Salehi, Mohammad Reza, Sadeghi, Ayoub
• Format: Journal Article
• Language: English
• Published: New York Springer US 01.09.2020; Springer Nature B.V
• Subjects: Arithmetic and logic units; Carbon nanotubes; Circuit design; Circuits and Systems; Computer simulation; Design optimization; Electrical Engineering; Electronics and Microelectronics; Engineering; Field effect transistors; Gates (circuits); Genetic algorithms; Image processing; Instrumentation; Logic circuits; Mathematical analysis; Power consumption; Process parameters; Semiconductor devices; Signal,Image and Speech Processing; Sorting algorithms; Field-effect transistor (CNTFET); Gate diffusion input (GDI) technique; Image processing; Carbon nanotube (CNT); Reversible logic-based magnitude arithmetic unit (RMAU); Non-dominated sorting genetic algorithm II (NSGA-II); Noise immunity; Energy-delay product (EDP)
• ISSN: 0278-081X; 1531-5878
• DOI: 10.1007/s00034-020-01382-1

Gate diffusion input (GDI) method using a simple cell makes it possible to design low-power logic gates with reduced chip area and less complexity. In this work, a novel design of single-bit optimized reversible logic-based magnitude arithmetic unit (RMAU) circuit, using appropriate standard reversible gates with carbon nanotube (CNT) field-effect transistors (CNTFETs), based on modified-GDI (m-GDI) method for nanoscales is presented. In order to optimize the performance of the proposed circuit, and to achieve minimum power consumption and propagation delay, transistor sizes are adjusted using the non-dominated sorting genetic algorithm II (NSGA-II) in MATLAB tool. The simulation results show improvement in evaluating the figure of merits in worst-case delay and power consumption of the proposed optimized arithmetic unit, in comparison with a non-optimized RMAU circuit using a similar design method but counterpart structures. The effects of different process parameters (such as the diameter of CNTs) and voltage and temperature (PVT) variations are extensively evaluated by the Monte Carlo procedure in standard 32 nm technology utilizing the Synopsys HSPICE simulator. According to the outcomes obtained, the proposed optimized RMAU circuit is robust against PVT variations and noise-tolerable criterions, compared to those competitors with similar design in non-optimized conditions. The proposed optimized and non-optimized circuits were used in image processing as real environment assessments, and results depicted their excellent ability in being implemented in various large reversible-based applications, such as future generations of FPGA chips and CNTFET-based computers.