A novel 3780-point FFT processor scheme for the time domain synchronous OFDM system

• Published in: Frontiers of information technology & electronic engineering Vol. 12; no. 12; pp. 1021 - 1030
• Main Authors: Leng, Ji-nan, Xie, Lei, Chen, Hui-fang, Wang, Kuang
• Format: Journal Article
• Language: English
• Published: Heidelberg SP Zhejiang University Press 01.12.2011; Springer Nature B.V
• Subjects: Algorithms; Architecture (computers); Communications Engineering; Computer Hardware; Computer Science; Computer Systems Organization and Communication Networks; Digital computers; Electrical Engineering; Electronics and Microelectronics; Fast Fourier transformations; Fourier transforms; Instrumentation; Iterative methods; Microprocessors; Modules; Multimedia; Multiplication; Networks; Orthogonal Frequency Division Multiplexing; PFA; Time domain; Time domain analysis; Time domain synchronous OFDM (TDS-OFDM); Winograd Fourier transform algorithm (WFTA); 3780; FFT; TN915.05; CoOrdinate Rotation DIgital Computer (CORDIC); Digital Multimedia/TV Broadcasting-Terrestrial (DMB-T)
• ISSN: 1869-1951; 2095-9184; 1869-196X; 2095-9230
• DOI: 10.1631/jzus.C1100071

The 3780-point FFT is a main component of the time domain synchronous OFDM （TDS-OFDM） system and the key technology in the Chinese Digital Multimedia/TV Broadcasting-Terrestrial （DMB-T） national standard. Sinc, e 3780 is not a power of 2, the classical radix-2 or radix-4 FFT algorithm cannot be applied directly. Hence, the Winograd Fourier transform algorithm （WFTA） and the Good-Thomas prime factor algorithm （PFA） are used to implement the 3780-point FFT processor. However, the structure based on WFTA and PFA has a large computational complexity and requires many DSPs in hardware implementation. In this paper, a novel 3780-point FFT processor scheme is proposed, in which a 60x63 iterative WFTA architecture with different mapping methods is imported to replace the PFA architecture, and an optimized CoOrdinate Rotation Digital Computer （CORDIC） module is used for the twiddle factor multiplications. Compared to the traditional scheme, our proposed 3780-point FFT processor scheme reduces the number of multiplications by 45% at the cost of 1% increase in the number of additions. All DSPs are replaced by the optimized CORDIC module and ROM. Simulation results show that the proposed 3780-point FFT processing scheme satisfies the requirement of the DMB-T standard, and is an efficient architecture for the TDS-OFDM system.