Design and implementation of a high sensitivity fully integrated passive UHF RFID tag

A fully integrated passive UHF RFID tag complying with the ISO 18000-6B protocol is presented, which includes an analog front-end, a baseband processor, and an EEPROM memory. To extend the communication range, a high efficiency differential-drive CMOS rectifier is adopted. A novel high performance v...

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Published inJournal of semiconductors Vol. 35; no. 10; pp. 146 - 151
Main Author 李守成 王新安 林科 沈劲鹏 张津海
Format Journal Article
LanguageEnglish
Published 01.10.2014
Subjects
Chips
CMOS
CMOS工艺
Dispersions
EEPROM存储器
Electric potential
Radio frequency identification
RFID标签
Semiconductors
UHF
Voltage
全集成
无源
设计
高灵敏度
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ISSN1674-4926
DOI10.1088/1674-4926/35/10/105010

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Summary:A fully integrated passive UHF RFID tag complying with the ISO 18000-6B protocol is presented, which includes an analog front-end, a baseband processor, and an EEPROM memory. To extend the communication range, a high efficiency differential-drive CMOS rectifier is adopted. A novel high performance voltage limiter is used to provide a stable limiting voltage, with a 172 mV voltage variation against temperature variation and process dispersion. The dynamic band-enhancement technique is used in the regulator circuit to improve the regulating capacity. A rail-to-rail hysteresis comparator is adopted to demodulate the signal correctly in any condition. The whole transponder chip is implemented in a 0.18μm CMOS process, with a die size of 900 × 800 μm2. Our measurement results show that the total power consumption of the tag chip is only 6.8 μW, with a sensitivity of -13.5 dBm.
Bibliography:UHF; RFID tag; differential-drive CMOS rectifier
A fully integrated passive UHF RFID tag complying with the ISO 18000-6B protocol is presented, which includes an analog front-end, a baseband processor, and an EEPROM memory. To extend the communication range, a high efficiency differential-drive CMOS rectifier is adopted. A novel high performance voltage limiter is used to provide a stable limiting voltage, with a 172 mV voltage variation against temperature variation and process dispersion. The dynamic band-enhancement technique is used in the regulator circuit to improve the regulating capacity. A rail-to-rail hysteresis comparator is adopted to demodulate the signal correctly in any condition. The whole transponder chip is implemented in a 0.18μm CMOS process, with a die size of 900 × 800 μm2. Our measurement results show that the total power consumption of the tag chip is only 6.8 μW, with a sensitivity of -13.5 dBm.
Li Shoucheng, Wang Xin＇an, Lin Ke, Shen Jinpeng, Zhang Jinhai（The Key Laboratory of Integrated Microsystems, Peking University Shenzhen Graduate School, Shenzhen 581055, China）
11-5781/TN
ObjectType-Article-1
SourceType-Scholarly Journals-1
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content type line 23
ISSN:1674-4926
DOI:10.1088/1674-4926/35/10/105010