Assessing ECG-QRS signal detection algorithm chip and simulation on several FPGAs

• Published in: Discover Computing Vol. 28; no. 1; p. 13
• Main Authors: Dhyani, Shikha, Kumar, Adesh, Choudhury, Sushabhan, Verma, Chaman, Illés, Zoltán
• Format: Journal Article
• Language: English
• Published: Dordrecht Springer Netherlands 25.02.2025; Springer Nature B.V
• Subjects: Algorithms; Computer Science; Data Mining and Knowledge Discovery; Data Structures and Information Theory; Depolarization; Electrocardiography; Field programmable gate arrays; Hardware description languages; Heart; Information Storage and Retrieval; Natural Language Processing (NLP); Pattern Recognition; Power consumption; Power management; Real time; S waves; Signal detection; Signal processing; VHSIC (circuits); Waveforms; QRS detection; Modelsim simulation; ECG signal processing; FPGA; Xilinx ISE; VHDL design
• ISSN: 2948-2992; 1386-4564; 2948-2992; 1573-7659
• DOI: 10.1007/s10791-025-09504-6

The electrocardiogram (ECG) is a diagnostic tool that records the electrical activity of the heart, providing information on the cardiac cycle. It is widely utilized in medical and healthcare settings for monitoring purposes. The QRS complex, which encompasses the Q wave, R wave, and S wave, is indicative of the depolarization of the ventricles. The QRS complex is a standard feature of ECG leads, and its waves vary depending on the lead position and the heart's electrical activity. The primary objective of this research endeavor has been to implement the Ahlstrom and Tompkins method's equations using Very High-Speed Integrated Circuit Hardware Description Language (VHDL). The aim is to develop a system capable of identifying the peak of two successive ECG waveforms. The hardware chip design for detecting the QRS complex in ECG signals was implemented using Xilinx ISE 14.7 and subsequently validated through successful simulation in Modelsim 10.0 software. The algorithm's performance is assessed on various FPGA platforms, specifically focusing on power consumption, latency, frequency, and hardware utilizations on Field-Programmable Gate Arrays (FPGAs) by Xilinx. The Virtex-7 FPGA has demonstrated superior performance when compared to other FPGA models, with an ideal delay value of 7.120 ns, power consumption of 1.95 mW, and operating frequency of 750 MHz. The novelty of this work lies in the scalable FPGA-based algorithm for QRS detection, which excels in switching speed and low power consumption across various FPGAs. This allows designers to integrate deep learning techniques for QRS detection and achieve hardware acceleration for real-time implementation.