A 10-bit 250 MSPS charge-domain pipelined ADC with replica controlled PVT insensitive BCT circuit

A low power 10-bit 250 MSPS charge-domain （CD） pipelined analog-to-digital converter （ADC） is introduced. The ADC is implemented in MOS bucket-brigade devices （BBDs） based CD pipelined architecture. A replica controlled boosted charge transfer （BCT） circuit is introduced to reject the influence of P...

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Published inJournal of semiconductors Vol. 36; no. 5; pp. 163 - 169
Main Author 黄嵩人 张鸿 陈珍海 朱泷 于宗光 钱宏文 郝跃
Format Journal Article
LanguageEnglish
Published 01.05.2015
Subjects
ADC
BCT
Charge transfer
Circuits
CMOS
Metal oxide semiconductors
MSPS
Noise levels
Power consumption
PVT
Sampling
Semiconductors
副本
控制
流水线
电荷转移
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ISSN1674-4926
DOI10.1088/1674-4926/36/5/055012

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Summary:A low power 10-bit 250 MSPS charge-domain （CD） pipelined analog-to-digital converter （ADC） is introduced. The ADC is implemented in MOS bucket-brigade devices （BBDs） based CD pipelined architecture. A replica controlled boosted charge transfer （BCT） circuit is introduced to reject the influence of PVT variations on the charge transfer process. Based on replica controlled BCT, the CD pipelined ADC is designed and realized in a 1P6M 0.18μm CMOS process. The ADC achieves an SFDR of 64.4 dB, an SNDR of 56.9 dB and an ENOB of 9.2 for a 9.9 MHz input; and an SFDR of 63.1 dB, an SNR of 55.2 dB, an SNDR of 54.5 dB and an ENOB of 8.7 for a 220.5 MHz input at full sampling rate. The DNL is ＋0.5/- 0.55 LSB and INL is ＋0.8/- 0.85 LSB. The power consumption of the prototype ADC is only 45 mW at 1.8 V supply and it occupies an active die area of 1.56 mm2.
Bibliography:pipelined analog-to-digital converter; charge domain; low power; charge transfer circuit
Huang Songren, Zhang Hong, Chen Zhenhai, Zhu Shuang, Yu Zongguang, Qian Hongwen, and Hao Yue 1 Wide Bandgap Semiconductor Technology Disciplines State Key Laboratory, Xidian University, Xi＇an 710071, China 2 School of Electronics and Information Engineering, Xi＇an Jiaotong University, Xi＇an 710049, China 3No. 58 Research Institute, China Electronic Technology Group Corporation, Wuxi 214035, China
A low power 10-bit 250 MSPS charge-domain （CD） pipelined analog-to-digital converter （ADC） is introduced. The ADC is implemented in MOS bucket-brigade devices （BBDs） based CD pipelined architecture. A replica controlled boosted charge transfer （BCT） circuit is introduced to reject the influence of PVT variations on the charge transfer process. Based on replica controlled BCT, the CD pipelined ADC is designed and realized in a 1P6M 0.18μm CMOS process. The ADC achieves an SFDR of 64.4 dB, an SNDR of 56.9 dB and an ENOB of 9.2 for a 9.9 MHz input; and an SFDR of 63.1 dB, an SNR of 55.2 dB, an SNDR of 54.5 dB and an ENOB of 8.7 for a 220.5 MHz input at full sampling rate. The DNL is ＋0.5/- 0.55 LSB and INL is ＋0.8/- 0.85 LSB. The power consumption of the prototype ADC is only 45 mW at 1.8 V supply and it occupies an active die area of 1.56 mm2.
11-5781/TN
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ISSN:1674-4926
DOI:10.1088/1674-4926/36/5/055012