A 2.5 GS/s 14-bit D/A converter with 8 to 1 MUX

A 2.5 GS/s 14-bit D/A converter（DAC） with 8 to 1 MUX is presented. This 14-bit DAC uses a ＂5＋9＂segment PMOS current-steering architecture. A bias circuit which ensures the PMOS current source obtains a larger output impedance under every PVT（process, source voltage and temperature） corner is also pr...

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Bibliographic Details
Published inJournal of semiconductors Vol. 37; no. 3; pp. 95 - 102
Main Author 张俊安 李广军 张瑞涛 付东兵 李皎雪 魏亚峰 阎波 刘军 李儒章
Format Journal Article
LanguageEnglish
Published 01.03.2016
Subjects
Architecture
Bias
Clocks
CMOS工艺
Converters
Corners
Current sources
D/A转换器
Electric potential
PMOS
Semiconductors
多路复用器
直接数字频率合成器
输出阻抗
驱动结构
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ISSN1674-4926
DOI10.1088/1674-4926/37/3/035004

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Summary:A 2.5 GS/s 14-bit D/A converter（DAC） with 8 to 1 MUX is presented. This 14-bit DAC uses a ＂5＋9＂segment PMOS current-steering architecture. A bias circuit which ensures the PMOS current source obtains a larger output impedance under every PVT（process, source voltage and temperature） corner is also presented. The8 to 1 MUX has a 3 stage structure, and a proper timing sequence is designed to ensure reliable data synthesis. A DEM function which is merged with a ＂5-31＂decoder is used to improve the DAC＇s dynamic performance. This DAC is embedded in a 2.5 GHz direct digital frequency synthesizer（DDS） chip, and is implemented in a 0.18 m CMOS technology, occupies 4.86 2. 28 mm-2 including bond pads（DAC only）, and the measured performance is SFDR 〉 40 d B（with and without DEM） for output signal frequency up to 1 GHz. Compared with other present published DACs with a non-analog-resample structure（means return-to-zero or quad-switch structure is unutilized）,this paper DAC＇s clock frequency（2.5 GHz） and higher output frequency SFDR（〉 40 d B, up to 1 GHz） has some competition.
Bibliography:11-5781/TN
PMOS current-steering D/A converter bias circuit high speed MUX dynamic element match（DEM）
A 2.5 GS/s 14-bit D/A converter（DAC） with 8 to 1 MUX is presented. This 14-bit DAC uses a ＂5＋9＂segment PMOS current-steering architecture. A bias circuit which ensures the PMOS current source obtains a larger output impedance under every PVT（process, source voltage and temperature） corner is also presented. The8 to 1 MUX has a 3 stage structure, and a proper timing sequence is designed to ensure reliable data synthesis. A DEM function which is merged with a ＂5-31＂decoder is used to improve the DAC＇s dynamic performance. This DAC is embedded in a 2.5 GHz direct digital frequency synthesizer（DDS） chip, and is implemented in a 0.18 m CMOS technology, occupies 4.86 2. 28 mm-2 including bond pads（DAC only）, and the measured performance is SFDR 〉 40 d B（with and without DEM） for output signal frequency up to 1 GHz. Compared with other present published DACs with a non-analog-resample structure（means return-to-zero or quad-switch structure is unutilized）,this paper DAC＇s clock frequency（2.5 GHz） and higher output frequency SFDR（〉 40 d B, up to 1 GHz） has some competition.
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ISSN:1674-4926
DOI:10.1088/1674-4926/37/3/035004