A 0.6 V 10 bit 1 MS/s monotonic switching SAR ADC with common mode stabilizer in 0.13μm CMOS

This paper presents a 0.6 V 10 bit successive approximation register （SAR） ADC design dedicated to the wireless sensor network application. It adopts a monotonic switching scheme in the DAC to save chip area and power consumption. The main drawback of the monotonic switching scheme is its large comm...

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Published inJournal of semiconductors Vol. 35; no. 5; pp. 98 - 104
Main Author 吕伟 罗多纳 梅逢城 杨家琪 姚立斌 贺林 林福江
Format Journal Article
LanguageEnglish
Published 01.05.2014
Subjects
ADC
CMOS
CMOS技术
Comparators
Constants
Consumption
Electric potential
Nyquist frequencies
SAR
Semiconductors
Switching
共模
切换方案
单调
稳定剂
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ISSN1674-4926
DOI10.1088/1674-4926/35/5/055006

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Summary:This paper presents a 0.6 V 10 bit successive approximation register （SAR） ADC design dedicated to the wireless sensor network application. It adopts a monotonic switching scheme in the DAC to save chip area and power consumption. The main drawback of the monotonic switching scheme is its large common mode shift and the associated comparator offset variation. Due to the limited headroom at the 0.6 V supply voltage, the conventional constant current biasing technique cannot be applied to the dynamic comparator. In this design, a common mode stabilizer is introduced to address this issue in low-voltage design. The effectiveness of this method is verified through both simulation and measurement results. Fabricated with 1P8M 0.13 μm CMOS technology, the proposed SAR ADC consumes 6.3 μW at 1 MS/s from a 0.6 V supply, and achieves 51.25 dB SNDR at the Nyquist frequency and FOM of 21 fJ/conversion-step. The core area is only 120 × 300 μm^2.
Bibliography:Lü Wei, Luo Duona, Mei Fengcheng, Yang Jiaqi, Yao Llbln, He Lin, Lin Fujiang（1 Department of Electronic Science and Technology, University of Science and Technology of China, Hefei 230027, China; 2Kunming Institute of Physics, Kunming 650223, China）
SAR ADC; monotonic switching; common mode stabilizer; comparator offset
11-5781/TN
This paper presents a 0.6 V 10 bit successive approximation register （SAR） ADC design dedicated to the wireless sensor network application. It adopts a monotonic switching scheme in the DAC to save chip area and power consumption. The main drawback of the monotonic switching scheme is its large common mode shift and the associated comparator offset variation. Due to the limited headroom at the 0.6 V supply voltage, the conventional constant current biasing technique cannot be applied to the dynamic comparator. In this design, a common mode stabilizer is introduced to address this issue in low-voltage design. The effectiveness of this method is verified through both simulation and measurement results. Fabricated with 1P8M 0.13 μm CMOS technology, the proposed SAR ADC consumes 6.3 μW at 1 MS/s from a 0.6 V supply, and achieves 51.25 dB SNDR at the Nyquist frequency and FOM of 21 fJ/conversion-step. The core area is only 120 × 300 μm^2.
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ISSN:1674-4926
DOI:10.1088/1674-4926/35/5/055006