FDTD based transition time dependent crosstalk analysis for coupled RLC interconnects
The performance of high density chips operating in the GHz range is mostly affected by on-chip interconnects. The interconnect delay depends on many factors, a few of them are inputs toggling patterns, line ＆ coupling parasitics, input rise/fall time and source/load characteristics. The transition t...
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| Published in | Journal of semiconductors Vol. 35; no. 5; pp. 69 - 73 |
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| Main Authors | , , |
| Format | Journal Article |
| Language | English |
| Published |
01.05.2014
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| Subjects | |
| Online Access | Get full text |
| ISSN | 1674-4926 |
| DOI | 10.1088/1674-4926/35/5/055001 |
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| Summary: | The performance of high density chips operating in the GHz range is mostly affected by on-chip interconnects. The interconnect delay depends on many factors, a few of them are inputs toggling patterns, line ＆ coupling parasitics, input rise/fall time and source/load characteristics. The transition time of the input is of prime importance in high speed circuits. This paper addresses the FDTD based analysis of transition time effects on functional and dynamic crosstalk. The analysis is carried out for equal and unequal transition times of coupled inputs. The analysis of the effects of unequal rise time is equally important because practically, it is quite common to have mismatching in the rise time of the signals transmitting through different length wires. To demonstrate the effects, two distributed RLC lines coupled inductively and capacitively are taken into consideration. The FDTD technique is used because it gives accurate results and carries time domain analysis of coupled lines. The number of lumps in SPICE simulations is considered the same as those of spatial segments. To validate the FDTD computed results, SPICE simulations are run and results are compared. A good agreement of the computed results has been observed with respect to SPICE simulated results. An average error of less than 3.2% is observed in the computation of the performance parameters using the proposed method. |
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| Bibliography: | The performance of high density chips operating in the GHz range is mostly affected by on-chip interconnects. The interconnect delay depends on many factors, a few of them are inputs toggling patterns, line ＆ coupling parasitics, input rise/fall time and source/load characteristics. The transition time of the input is of prime importance in high speed circuits. This paper addresses the FDTD based analysis of transition time effects on functional and dynamic crosstalk. The analysis is carried out for equal and unequal transition times of coupled inputs. The analysis of the effects of unequal rise time is equally important because practically, it is quite common to have mismatching in the rise time of the signals transmitting through different length wires. To demonstrate the effects, two distributed RLC lines coupled inductively and capacitively are taken into consideration. The FDTD technique is used because it gives accurate results and carries time domain analysis of coupled lines. The number of lumps in SPICE simulations is considered the same as those of spatial segments. To validate the FDTD computed results, SPICE simulations are run and results are compared. A good agreement of the computed results has been observed with respect to SPICE simulated results. An average error of less than 3.2% is observed in the computation of the performance parameters using the proposed method. Devendra Kumar Sharma, Brajesh Kumar Kaushik, R. K. Sharma（1 Department of ECE, Meerut Institute of Engineering and Technology, Meerut, India; 2 Department of Electronics ＆ Computer Engineering, Indian Institute of Technology, Roorkee, India ;3 Department of ECE, National Institute of Technology, Kurukshetra, Haryana, India） 11-5781/TN FDTD; transition time; crosstalk noise; delay; coupled interconnects ObjectType-Article-1 SourceType-Scholarly Journals-1 ObjectType-Feature-2 content type line 23 |
| ISSN: | 1674-4926 |
| DOI: | 10.1088/1674-4926/35/5/055001 |