Dual-gate lateral double-diffused metal—oxide semiconductor with ultra-low specific on-resistance

A new high voltage trench lateral double-diffused metal–oxide semiconductor （LDMOS） with ultra-low specific onresistance （R on,sp ） is proposed. The structure features a dual gate （DG LDMOS）： a planar gate and a trench gate inset in the oxide trench. Firstly, the dual gate can provide a dual conduct...

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Published inChinese physics B Vol. 22; no. 4; pp. 531 - 536
Main Author 范杰 汪志刚 张波 罗小蓉
Format Journal Article
LanguageEnglish
Published 01.04.2013
Subjects
Channels
Equivalence
Gates
LDMOS
Metal oxide semiconductors
Metal oxides
Oxides
Semiconductors
Trenches
Voltage
仿真结果
低导通电阻
击穿电压
双扩散
双门
电场分布
金属氧化物半导体
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ISSN1674-1056
2058-3834
1741-4199
DOI10.1088/1674-1056/22/4/048501

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Summary:A new high voltage trench lateral double-diffused metal–oxide semiconductor （LDMOS） with ultra-low specific onresistance （R on,sp ） is proposed. The structure features a dual gate （DG LDMOS）： a planar gate and a trench gate inset in the oxide trench. Firstly, the dual gate can provide a dual conduction channel and reduce R on,sp dramatically. Secondly, the oxide trench in the drift region modulates the electric field distribution and reduces the cell pitch but still can maintain comparable breakdown voltage （BV）. Simulation results show that the cell pitch of the DG LDMOS can be reduced by 50% in comparison with that of conventional LDMOS at the equivalent BV; furthermore, R on,sp of the DG LDMOS can be reduced by 67% due to the smaller cell pitch and the dual gate.
Bibliography:Fan Jie , Wang Zhi-Gang, Zhang Bo, Luo Xiao-Rong （State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, China）
breakdown voltage; specific on-resistance; dual gate; oxide trench
A new high voltage trench lateral double-diffused metal–oxide semiconductor （LDMOS） with ultra-low specific onresistance （R on,sp ） is proposed. The structure features a dual gate （DG LDMOS）： a planar gate and a trench gate inset in the oxide trench. Firstly, the dual gate can provide a dual conduction channel and reduce R on,sp dramatically. Secondly, the oxide trench in the drift region modulates the electric field distribution and reduces the cell pitch but still can maintain comparable breakdown voltage （BV）. Simulation results show that the cell pitch of the DG LDMOS can be reduced by 50% in comparison with that of conventional LDMOS at the equivalent BV; furthermore, R on,sp of the DG LDMOS can be reduced by 67% due to the smaller cell pitch and the dual gate.
11-5639/O4
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SourceType-Scholarly Journals-1
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ISSN:1674-1056
2058-3834
1741-4199
DOI:10.1088/1674-1056/22/4/048501