An On-Chip Architectural Framework Design for Achieving High-Throughput Multi-Channel High-Bandwidth Memory Access in Field-Programmable Gate Array Systems

• Published in: Electronics (Basel) Vol. 14; no. 3; p. 466
• Main Authors: Kong, Xiangcong, Zhu, Zixuan, Feng, Chujun, Zhu, Yongxin, Zheng, Xiaoying
• Format: Journal Article
• Language: English
• Published: Basel MDPI AG 01.02.2025
• Subjects: Bandwidths; Data processing; Digital integrated circuits; Efficiency; Field programmable gate arrays; Multichannel communication; Radio astronomy; System on chip; Workloads
• ISSN: 2079-9292; 2079-9292
• DOI: 10.3390/electronics14030466

The integration of High-Bandwidth Memory (HBM) into Field-Programmable Gate Arrays (FPGAs) has significantly enhanced data processing capabilities. However, the segmentation of HBM into 32 pseudo-channels, each managed by a performance-limited crossbar, imposes a significant bottleneck on data throughput. To overcome this challenge, we propose a transparent HBM access framework that integrates a non-blocking network-on-chip (NoC) module and fine-grained burst control transmission, enabling efficient multi-channel memory access in HBM. Our Omega-based NoC achieves a throughput of 692 million packets per second, surpassing state-of-the-art solutions. When implemented on the Xilinx Alveo U280 FPGA board, the proposed framework attains near-maximum single-channel write bandwidth, delivering 12.94 GB/s in many-to-many unicast communication scenarios, demonstrating its effectiveness in optimizing memory access for high-performance applications.