Design of a digit-serial multiplier over GF(2m) using a karatsuba algorithm

• Published in: Journal of the Chinese Institute of Engineers Vol. 42; no. 7; pp. 602 - 612
• Main Authors: Lee, Trong-Yen, Liu, Min-Jea, Huang, Chia-Han, Fan, Chia-Chen, Tsai, Chia-Chun, Wu, Haixia
• Format: Journal Article
• Language: English
• Published: Taylor & Francis 03.10.2019
• Subjects: Digit-serial multiplier; finite-field; Karatsuba algorithm
• ISSN: 0253-3839; 2158-7299
• DOI: 10.1080/02533839.2019.1644200

A Karatsuba algorithm (KA) is used for highly accurate multiplication using a divide and conquer approach. A new approach to a polynomial digit-serial multiplier that uses an optimal digit size (d) for KA decomposition has recently been proposed. In this study, the proposed architecture uses three small multipliers to derive an optimal digit size (d) for the case of trinomial based fields. Using the proposed KA decomposition, this study establishes five types of sub-quadratic multipliers, which are, the recombined m-bit exponentiation multipliers using a KA. The theoretical results show that the proposed polynomial exponentiation multipliers that use a KA have a value of (d × m)/2 and involve significantly less time and area complexity than existing digit-serial multipliers. The simulation results for the proposed method demonstrate a respective 68.20%, 77.37%, 72%, 83.18%, 36.66% decrease in area × time over GF(2 36 ), GF(2 84 ), GF(2 126 ), GF(2 204 ) and GF(2 340 ).