Two-dimensional mapping method for evaluation of phase-locked loop signal in cryo-CMOS qubit control circuits

• Published in: Japanese Journal of Applied Physics Vol. 64; no. 7; pp. 76503 - 76508
• Main Authors: Matsuoka, Ryutaro, Wachi, Yusuke, Tsuchiya, Ryuta, Mizuno, Hiroyuki, Kodera, Tetsuo
• Format: Journal Article
• Language: English
• Published: Tokyo IOP Publishing 01.07.2025; Japanese Journal of Applied Physics
• Subjects: Configuration management; Control systems; Cryo-CMOS; Frequency synthesizers; Mapping; Noise measurement; Phase locked loops; Phase noise; phase-locked loop; Qubits (quantum computing); Signal quality; spin qubit; Synthesizers
• ISSN: 0021-4922; 1347-4065
• DOI: 10.35848/1347-4065/adeb23

Cryogenic control systems are essential for integrating semiconductor spin qubits, and reducing phase noise in phase-locked loop (PLL) frequency synthesizers is critical for high-fidelity spin qubit control. Conventional single-frequency phase noise evaluation methods are not suitable for the multi-frequency demands of spin qubit architectures. To address this, we develop a two-dimensional (2D) phase noise mapping method that evaluates spectral purity as a function of both output and offset frequency. Using a cryogenic fractional-N PLL, we measure phase noise under different reference frequencies and observe frequency dependence of spurious signal. Simulations based on these measurements show infidelity variations up to ∼0.08% across 19.60–20.40 GHz. Our method enables identification of optimal signal configurations and supports resource-efficient design of control electronics. This framework contributes to a practical tool for scaling spin qubit systems and improving signal quality in cryogenic quantum processors.