Scalar Replacement in the Presence of Multiple Write Accesses with Non-constant Reuse Distances

• Published in: IPSJ Transactions on System and LSI Design Methodology Vol. 18; pp. 10 - 18
• Main Author: Seto, Kenshu
• Format: Journal Article
• Language: English
• Published: Tokyo Information Processing Society of Japan 01.01.2025; Japan Science and Technology Agency
• Subjects: Accelerators; Gate counting; High level synthesis; memory access optimization; Optimization; scalar replacement
• ISSN: 1882-6687; 1882-6687
• DOI: 10.2197/ipsjtsldm.18.10

High-level synthesis (HLS) reduces design time of domain-specific accelerators from loop nests. Usually, naive usage of HLS leads to accelerators with insufficient performance, so very time-consuming manual optimizations of input programs are necessary in such cases. Scalar replacement is a promising automatic memory access optimization that removes redundant memory accesses. However, it cannot handle loops with multiple write accesses to the same array, which poses a severe limitation of its applicability. In addition, it is difficult to automatically apply scalar replacement to memory accesses with non-constant reuse distances. In this paper, we propose a novel memory access optimization technique that overcomes these existing limitations. Experimental results show that the proposed method achieves 2.14x performance gain on average with decreased total gate count of 5% for the benchmark programs which the state-of-the-art memory optimization techniques cannot optimize.