Novel substrate trigger SCR-LDMOS stacking structure for high-voltage ESD protection application

A novel substrate trigger semiconductor control rectifier-laterally diffused metal-oxide semiconductor （STSCR- LDMOS） stacked structure is proposed and simulated using the transimission line pulser （TLP） multiple-pulse simulation method in a 0.35μm, 60-V biploar-CMOS-DMOS （BCD） process without addit...

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Bibliographic Details
Published inChinese physics B Vol. 24; no. 4; pp. 394 - 398
Main Author 马金荣 乔明 张波
Format Journal Article
LanguageEnglish
Published IOP Publishing 01.04.2015
Subjects
Electric potential
electrostatic discharge
Electrostatic discharges
ESD保护器件
high holding voltage
latch-up
Metal oxide semiconductors
Metal oxides
Semiconductors
Simulation
Stacking
STSCR-LDMOS
Voltage
叠层结构
堆叠
应用程序
衬底
触发电压
金属氧化物半导体
高压
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ISSN1674-1056
2058-3834
1741-4199
DOI10.1088/1674-1056/24/4/047303

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Summary:A novel substrate trigger semiconductor control rectifier-laterally diffused metal-oxide semiconductor （STSCR- LDMOS） stacked structure is proposed and simulated using the transimission line pulser （TLP） multiple-pulse simulation method in a 0.35μm, 60-V biploar-CMOS-DMOS （BCD） process without additional masks. On account of a very low holding voltage, it is susceptible to latch-up-like danger for the semiconductor control rectifier-laterally diffused metaloxide semiconductor （SCR-LDMOS） in high-voltage electro-static discharge （ESD） protection applications. Although the conventional stacking structure has achieved strong latch-up immunity by increasing holding voltage, excessive high trigger voltage does not meet requirements for an ESD protection device. The holding voltage of the proposed stacked structure is proportional to the stacking number, whereas the trigger voltage remains nearly the same. A high holding voltage of 30.6 V and trigger voltage of 75.4 V are achieved.
Bibliography:electrostatic discharge, high holding voltage, latch-up, STSCR-LDMOS
A novel substrate trigger semiconductor control rectifier-laterally diffused metal-oxide semiconductor （STSCR- LDMOS） stacked structure is proposed and simulated using the transimission line pulser （TLP） multiple-pulse simulation method in a 0.35μm, 60-V biploar-CMOS-DMOS （BCD） process without additional masks. On account of a very low holding voltage, it is susceptible to latch-up-like danger for the semiconductor control rectifier-laterally diffused metaloxide semiconductor （SCR-LDMOS） in high-voltage electro-static discharge （ESD） protection applications. Although the conventional stacking structure has achieved strong latch-up immunity by increasing holding voltage, excessive high trigger voltage does not meet requirements for an ESD protection device. The holding voltage of the proposed stacked structure is proportional to the stacking number, whereas the trigger voltage remains nearly the same. A high holding voltage of 30.6 V and trigger voltage of 75.4 V are achieved.
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ISSN:1674-1056
2058-3834
1741-4199
DOI:10.1088/1674-1056/24/4/047303