Synthesizing linear array algorithms from nested FOR loop algorithms

The mapping of algorithms structured as depth-p nested FOR loops into special-purpose systolic VLSI linear arrays is addressed. The mappings are done by using linear functions to transform the original sequential algorithms into a form suitable for parallel execution on linear arrays. A feasible map...

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Bibliographic Details
Published inIEEE transactions on computers Vol. 37; no. 12; pp. 1578 - 1598
Main Authors Lee Peizong, Kedem, Z.M.
Format Journal Article
LanguageEnglish
Published New York, NY IEEE 01.12.1988
Institute of Electrical and Electronics Engineers
Subjects
Algorithmics. Computability. Computer arithmetics
Applied sciences
Computer science; control theory; systems
Exact sciences and technology
Theoretical computing
Very large scale integration
VLSI circuit
Integrated circuit
Data dependence
Parallel processing
Systolic network
Algorithm
Implementation
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ISSN0018-9340
DOI10.1109/12.9735

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Summary:The mapping of algorithms structured as depth-p nested FOR loops into special-purpose systolic VLSI linear arrays is addressed. The mappings are done by using linear functions to transform the original sequential algorithms into a form suitable for parallel execution on linear arrays. A feasible mapping is derived by identifying formal criteria to be satisfied by both the original sequential algorithm and the proposed transformation function. The methodology is illustrated by synthesizing algorithms for matrix multiplication and a version of the Warshall-Floyd transitive closure algorithm.< >
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ISSN:0018-9340
DOI:10.1109/12.9735