Diagnostic Fail Data Minimization Using an N -Cover Algorithm

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 24; no. 3; pp. 1198 - 1202
• Main Authors: Bodhe, Shraddha, Amyeen, M. Enamul, Pomeranz, Irith, Venkataraman, Srikanth
• Format: Journal Article
• Language: English
• Published: IEEE 01.03.2016
• Subjects: Algorithm design and analysis; Algorithms; Circuit faults; Counting; Data mining; Data models; Defect diagnosis; Diagnosis; Effectiveness; fail data collection; Fault diagnosis; greedy set cover; Integrated circuit modeling; Integrated circuits; Methodology; Minimization; testing; Very large scale integration; Defect diagnosis; greedy set cover; fail data collection; testing
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2015.2432717

With the increasing transistor count and design complexity of modern integrated circuits, a large volume of fail data is collected by the tester for a failing die. This fail data is analyzed by a diagnosis procedure to obtain information about the defects in the die that caused it to fail. However, large portions of the fail data are not necessary for diagnosis. As a result, the diagnosis procedure spends time analyzing unnecessary data, thus decreasing its speed and throughput. We present a methodology to minimize the amount of fail data that is provided to the diagnosis procedure without compromising the diagnosis accuracy (DA). Our methodology evaluates the outputs at which the tests failed to eliminate noncontributing failing tests. The efficacy of our algorithm is demonstrated using fail data from industry fabricated chips. The experimental results show that, on average, our algorithm achieves fail data minimization of 40% while maintaining an average DA of 95%. The speed of the diagnosis procedure is increased by 39%.