A secure scan architecture using dynamic key to thwart scan-based side-channel attacks

• Published in: Microelectronics Vol. 143; p. 106050
• Main Authors: Wang, Weizheng, Chen, Jinhai, Pan, Xianmin
• Format: Journal Article
• Language: English
• Published: Elsevier Ltd 01.01.2024
• Subjects: Cryptographic chip; Dynamic key generation; Hardware security; Scan-based attack; Scan-based attack; Cryptographic chip; Hardware security; Dynamic key generation
• ISSN: 1879-2391
• DOI: 10.1016/j.mejo.2023.106050

Scan testing is widely used in the rigorous testing of modern integrated circuits. However, the controllable and observable nature of the scan design also provides opportunities for attackers who can utilise this structure to steal secret information stored in the chip. This paper proposes a secure Design for Testability (DFT) architecture to prevent scan-based attacks. The scheme uses a modified Linear Feedback Shift Register (LFSR) to dynamically generate keys for the scan design key generator and verifies them against a specific selection of test key flip-flops in the original scan chain, and locks the control signals by transmitting the outputs of the verification comparisons to a OR gate. When the test authorisation key is correct, the circuit performs a normal scan operation; otherwise, the circuit enters an abnormal test mode and the data in the scan chain is dynamically obfuscated, thus preventing from observing valid data or deriving an encryption key through the output of the scan chain.