Generating synthetic benchmark circuits for accelerated life testing of field programmable gate arrays using genetic algorithm and particle swarm optimization

• Published in: Applied soft computing Vol. 27; pp. 179 - 190
• Main Authors: Srivani, L., Krishna Giri, N.H.V., Ganesh, Shankar, Kamakoti, V.
• Format: Journal Article
• Language: English
• Published: Elsevier B.V 01.02.2015
• Subjects: Accelerated life testing (ALT); Field programmable gate arrays (FPGA); Genetic algorithms (GA); Particle swarm optimization (PSO); Synthetic benchmark circuits (SBC); Genetic algorithms (GA); Field programmable gate arrays (FPGA); Synthetic benchmark circuits (SBC); Accelerated life testing (ALT); Particle swarm optimization (PSO)
• ISSN: 1568-4946; 1872-9681
• DOI: 10.1016/j.asoc.2014.11.002

[Display omitted] •Generating circuits for accelerated life testing of field programmable gate arrays.•The problem involves multi-variable optimization.•Proposed a genetic algorithm for the purpose mentioned above.•Proved empirically that particle swarm optimization can be used to enhance the quality of results yielded by a GA.•Showed that GA aided by PSO not only reduces time (from months to hours) but can also yield better results than the hand-crafted SBC. Accelerated life testing (ALT) of a field programmable gate array (FPGA) requires it to be configured with a circuit that satisfies multiple criteria. Hand-crafting such a circuit is a herculean task as many components of the criteria are orthogonal to each other demanding a complex multivariate optimization. This paper presents an evolutionary algorithm aided by particle swarm optimization methodology to generate synthetic benchmark circuits (SBC) that can be used for ALT of FPGAs. The proposed algorithm was used to generate a SBC for ALT of a commercial FPGA. The generated SBC when compared with a hand-crafted one, demonstrated to be more suitable for ALT, measured in terms of meeting the multiple criteria. The SBC generated by the proposed technique utilizes 8.37% more resources; operates at a maximum frequency which is 40% higher; and has 7.75% higher switching activity than the hand-crafted one reported in the literature. The hand-crafted circuit is very specific to the particular device of that family of FPGAs, whereas the proposed algorithm is device-independent. In addition, it took several man months to hand-craft the SBC, whereas the proposed algorithm took less than half-a-day.