Using the multistage cube network topology in parallel supercomputers

• Published in: Proceedings of the IEEE Vol. 77; no. 12; pp. 1932 - 1953
• Main Authors: Siegel, H.J., Nation, W.G., Kruskal, C.P., Napolitano, L.M.
• Format: Journal Article
• Language: English
• Published: United States IEEE 01.12.1989
• Subjects: Computational modeling; COMPUTER NETWORKS; COMPUTERS; Concurrent computing; Costs; DIGITAL COMPUTERS; GENERAL AND MISCELLANEOUS//MATHEMATICS, COMPUTING, AND INFORMATION SCIENCE; HYPERCUBE COMPUTERS; Intelligent networks; Large-scale systems; MATHEMATICS; Missiles; Network topology; PARALLEL PROCESSING; PROGRAMMING 990200 > Mathematics & Computers; SUPERCOMPUTERS; Switches; TOPOLOGY
• ISSN: 0018-9219; 1558-2256
• DOI: 10.1109/5.48833

A critical component of any large-scale parallel processing system is the interconnection network that provides a means for communication along the system's processors and memories. Attributes of the multistage cube topology that have made it an effective basis for interconnection networks and the subject of much ongoing research are reviewed. These attributes include O(N log/sub 2/N) cost for an N-input/output network, decentralized control, a variety of implementation options, good data-permuting capability to support single-instruction-stream/multiple-data-stream (SIMD) parallelism, good throughput to support multiple-instruction-stream/multiple-data-stream (MIMD) parallelism, and ability to be partitioned into independent subnetworks to support reconfigurable systems. Examples of existing systems that use multistage cube networks are considered. The multistage cube topology can be converted into a single-stage network by associating with each switch in the network a processor (and a memory). Properties of systems that use the multistage cube network in this way are examined.< >