Deep Learning-Aided Belief Propagation Decoder for Polar Codes

• Published in: IEEE journal on emerging and selected topics in circuits and systems Vol. 10; no. 2; pp. 189 - 203
• Main Authors: Xu, Weihong, Tan, Xiaosi, Be'ery, Yair, Ueng, Yeong-Luh, Huang, Yongming, You, Xiaohu, Zhang, Chuan
• Format: Journal Article
• Language: English
• Published: Piscataway IEEE 01.06.2020; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; ASIC implementation; Back propagation; Belief propagation; belief propagation (BP); Circuits and systems; CMOS; Codes; Complexity theory; concatenated codes; Decoders; Decoding; Deep learning; Error correction; Hardware; Iterative decoding; Machine learning; Optimization; Polar codes; Propagation; Throughput
• ISSN: 2156-3357; 2156-3365
• DOI: 10.1109/JETCAS.2020.2995962

This paper presents deep learning (DL) methods to optimize polar belief propagation (BP) decoding and concatenated LDPC-polar codes. First, two-dimensional offset Min-Sum (2-D OMS) decoding is proposed to improve the error-correction performance of existing normalized Min-Sum (NMS) decoding. Two optimization methods used in DL, namely back-propagation and stochastic gradient descent, are exploited to derive the parameters of proposed algorithms. Numerical results demonstrate that there is no performance gap between 2-D OMS and exact BP on various code lengths. Then the concatenated OMS algorithms with low complexity are presented for concatenated LDPC-polar codes. As a result, the optimized concatenated OMS decoding yields error-correction performance with CRC-aided successive cancellation list (CA-SCL) decoder of list size 2 on length-1024 polar codes. In addition, the efficient hardware architectures of scalable polar OMS decoder are described and the proposed decoder is reconfigurable to support three code lengths (<inline-formula> <tex-math notation="LaTeX">N= 256, 512, 1024 </tex-math></inline-formula>) and two decoding algorithms (2-D OMS and concatenated OMS). The polar OMS decoder implemented on 65 nm CMOS technology achieves a maximum coded throughput of 5.4 Gb/s at <inline-formula> <tex-math notation="LaTeX">E_{b}/N_{0} = 4 </tex-math></inline-formula> dB for code length 1024 and 7.5 Gb/s at <inline-formula> <tex-math notation="LaTeX">E_{b}/N_{0} = 3.5 </tex-math></inline-formula> dB for code length 256, which are comparable to the state-of-the-art polar BP decoders. Moreover, a 5.1 Gb/s throughput at <inline-formula> <tex-math notation="LaTeX">E_{b}/N_{0} = 4 </tex-math></inline-formula> dB is achieved under concatenated OMS decoding mode for code length 1024 with a latency of 200 ns, which is superior to existing CA-SCL decoders that have similar error-correction performance.