Scalable Digital CMOS Comparator Using a Parallel Prefix Tree

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 21; no. 11; pp. 1989 - 1998
• Main Authors: Abdel-Hafeez, Saleh, Gordon-Ross, Ann, Parhami, Behrooz
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.11.2013; Institute of Electrical and Electronics Engineers
• Subjects: Adders; Applied sciences; Clocks; CMOS integrated circuits; Computer architecture; Delay; Design. Technologies. Operation analysis. Testing; Electronics; Exact sciences and technology; High-speed arithmetic; high-speed wide-bit comparator architecture; Integrated circuits; Logic gates; parallel prefix tree structure; Power demand; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Performance evaluation; VLSI circuit; Scalability; Worst case method; High-speed arithmetic; Tree structure; Parallel architectures; Proceedings; Fan; High power; Energy dissipation; Interconnection; Complementary MOS technology; high-speed wide-bit comparator architecture; Integrated circuit; parallel prefix tree structure; SPICE; Fan out; Delay time; Reconfigurable architectures; Comparator circuit; Comparative study
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2012.2222453

We present a new comparator design featuring wide-range and high-speed operation using only conventional digital CMOS cells. Our comparator exploits a novel scalable parallel prefix structure that leverages the comparison outcome of the most significant bit, proceeding bitwise toward the least significant bit only when the compared bits are equal. This method reduces dynamic power dissipation by eliminating unnecessary transitions in a parallel prefix structure that generates the N-bit comparison result after (log 4 N)+(log 16 N)+4 CMOS gate delays. Our comparator is composed of locally interconnected CMOS gates with a maximum fan-in and fan-out of five and four, respectively, independent of the comparator bitwidth. The main advantages of our design are high speed and power efficiency, maintained over a wide range. Additionally, our design uses a regular reconfigurable VLSI topology, which allows analytical derivation of the input-output delay as a function of bitwidth. HSPICE simulation for a 64-b comparator shows a worst case input-output delay of 0.86 ns and a maximum power dissipation of 7.7 mW using 0.15- μm TSMC technology at 1 GHz.