Pull up transistor folding

A polynomial-time algorithm for the pull up transistor assignment problem is developed, and it is shown that the interval selection and interval selection with pull up transistor assignment problems are NP-hard. Heuristics for these problems are proposed and compared with that proposed by C. Lursins...

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Bibliographic Details
Published inIEEE transactions on computer-aided design of integrated circuits and systems Vol. 9; no. 5; pp. 512 - 521
Main Authors Li, W.-N., Sahni, S.
Format Journal Article
LanguageEnglish
Published New York, NY IEEE 01.05.1990
Institute of Electrical and Electronics Engineers
Subjects
Applied sciences
Computer science
Design. Technologies. Operation analysis. Testing
Electronics
Exact sciences and technology
Integrated circuits
NP-hard problem
Polynomials
Programmable logic arrays
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Improvement
Performance characteristic
Heuristic method
NP complete problem
Transistor
Performance
Algorithm
Computer aided design
Comparative study
Polynomial time
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ISSN0278-0070
DOI10.1109/43.55181

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Summary:A polynomial-time algorithm for the pull up transistor assignment problem is developed, and it is shown that the interval selection and interval selection with pull up transistor assignment problems are NP-hard. Heuristics for these problems are proposed and compared with that proposed by C. Lursinsap and G. Gajski (ibid., vol.7, no.8, p.887-96, 1988).< >
Bibliography:ObjectType-Article-2
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ObjectType-Feature-1
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ISSN:0278-0070
DOI:10.1109/43.55181