Design of Approximate Booth Squarer for Error-Tolerant Computing

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 28; no. 5; pp. 1230 - 1241
• Main Authors: Manikantta Reddy, K., Vasantha, M. H., Nithin Kumar, Y. B., Dwivedi, Devesh
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.05.2020; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Adders; Approximate Booth squarer; approximate computing; approximate partial product generator for squarer (APPGS); CMOS; Complexity theory; Compressors; Computation; Computer simulation; Delay; Delays; Encoding; Error recovery; Generators; Hardware; input signal rearrangement (ISR); Noise levels; signal probability; Signal to noise ratio
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2020.2976131

To explore the benefits of approximate computing, this article proposes an approximate partial product generator for squarer (APPGS). Using APPGS, three designs of approximate radix-4 Booth squarers (ABS1, ABS2, and ABS3) are proposed. APPGS produces approximate partial products in <inline-formula> <tex-math notation="LaTeX">r </tex-math></inline-formula> number of least significant columns of the partial product matrix. ABS2 and ABS3 utilize approximate adders and compressors with a novel input signal rearrangement method for the accumulation of approximate partial products. Moreover, the ABS3 features an error recovery module at <inline-formula> <tex-math notation="LaTeX">k </tex-math></inline-formula> number of most significant columns of the approximate partial products. The proposed squarers with different values of <inline-formula> <tex-math notation="LaTeX">r </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">k </tex-math></inline-formula> are simulated using 45-nm CMOS technology. The results indicate that the proposed squarers achieve optimized performance for both hardware and accuracy metrics. Compared to the exact Booth squarer, the 16-bit ABS1 with <inline-formula> <tex-math notation="LaTeX">r=16 </tex-math></inline-formula> achieves a reduction of 13.6%, 22.2%, and 13.7% in power, delay, and area, respectively, with a normalized mean error distance (NMED) of <inline-formula> <tex-math notation="LaTeX">4.6\times 10^{-6} </tex-math></inline-formula>. The ABS2 has power, delay, and area savings of 25.8%, 33.8%, and 19.8%, respectively, with an NMED of <inline-formula> <tex-math notation="LaTeX">7.2\times 10^{-6} </tex-math></inline-formula>. The ABS3 with <inline-formula> <tex-math notation="LaTeX">k=6 </tex-math></inline-formula> has 18.5% reduction in power, 29.4% reduction in delay, and 16.9% reduction in area with an NMED of <inline-formula> <tex-math notation="LaTeX">0.56\times 10^{-6} </tex-math></inline-formula>. The performance of the proposed squarers is evaluated with a telecommunication application, where the ABS3 with <inline-formula> <tex-math notation="LaTeX">k=6 </tex-math></inline-formula> produces an output signal with a signal-to-noise ratio of 32.45 dB.