Low-Complexity Interval Passing Algorithm and VLSI Architecture for Binary Compressed Sensing

Binary compressed sensing (BCS), in which signals of interest have binary values, finds applications in areas including fault detection and wireless sensor networks. In this article, a low-complexity VLSI architecture for BCS based on interval passing algorithm is proposed. Moreover, the algorithm i...

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Published inIEEE transactions on very large scale integration (VLSI) systems Vol. 28; no. 5; pp. 1283 - 1291
Main Authors Kalipatnapu, Shantharam, Chakrabarti, Indrajit
Format Journal Article
LanguageEnglish
Published New York IEEE 01.05.2020
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
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ISSN1063-8210
1557-9999
DOI10.1109/TVLSI.2020.2967477

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Summary:Binary compressed sensing (BCS), in which signals of interest have binary values, finds applications in areas including fault detection and wireless sensor networks. In this article, a low-complexity VLSI architecture for BCS based on interval passing algorithm is proposed. Moreover, the algorithm is modified in order to reduce its complexity without significant loss in performance, and its corresponding VLSI architecture is proposed. Binary low-density parity check (LDPC) matrices based on finite geometry have been used as measurement matrices. The proposed VLSI architectures have been synthesized in both ASIC and field-programmable gate array (FPGA) platforms. The hardware consumption of the proposed designs is independent of sparsity values. Moreover, the proposed architectures offer high frequency of operation and low reconstruction time when compared to the state-of-the-art designs. Specifically, the 65-nm ASIC realization operates at a maximum frequency of 500 and 666.67 MHz and offer a reconstruction time of 6.3 and 4.7 ns, respectively, for a <inline-formula> <tex-math notation="LaTeX">64\times 256 </tex-math></inline-formula> deterministic measurement matrix.
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ISSN:1063-8210
1557-9999
DOI:10.1109/TVLSI.2020.2967477