A New Hardware-Efficient Spectrum-Sensor VLSI Architecture for Data-Fusion-Based Cooperative Cognitive-Radio Network

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 29; no. 4; pp. 760 - 773
• Main Authors: Chaurasiya, Rohit B., Shrestha, Rahul
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.04.2021; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; Application specific integrated circuits; Application-specific integrated circuit (ASIC); CMOS; Cognitive radio; cognitive radio (CR); Data integration; digital architecture; False alarms; Field programmable gate arrays; field-programmable gate array (FPGA); Hardware; Integrated circuits; Iterative methods; Multisensor fusion; Performance degradation; Power consumption; Very large scale integration; VLSI; VLSI algorithm
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2021.3055344

This article presents a hardware-friendly algorithm and architecture for cooperative spectrum sensing (CSS) in the data-fusion-based cognitive-radio (CR) network. The proposed VLSI-algorithm is based on the iterative power method and deflation technique that alleviate the computational complexity of conventional CSS algorithm with minimal performance degradation. In this work, a new hardware-efficient VLSI architecture of cooperative spectrum sensor (CSR) for the data-fusion center is presented, which supports up to six secondary users in the cooperative CR network. Its performance analysis under fading channel environment has been carried out where it delivers 0.8 detection probability (<inline-formula> <tex-math notation="LaTeX">P_{d} </tex-math></inline-formula>) at −8 dB of channel SNR with a false alarm rate of 0.1. It shows the minimum performance degradation of 0.057 dB at <inline-formula> <tex-math notation="LaTeX">P_{d} = 0.88 </tex-math></inline-formula> compared to the conventional algorithm. The suggested CSR architecture has been application-specific integrated circuit (ASIC)-synthesized and postlayout simulated in UMC 90 nm-CMOS process. Thus, it occupies 2.4 mm 2 of the core area, consumes 36 mW of total power, and delivers a low sensing time of <inline-formula> <tex-math notation="LaTeX">60.41~\mu \text{s} </tex-math></inline-formula> while operating at a maximum clock frequency of 87.7 MHz. Comparison with the reported works indicates that the proposed design requires 40.3% lesser area, and it is 41% hardware efficient than the conventional implementation. Eventually, this design has been field-programmable gate array (FPGA) prototyped, and its functionality is verified in the real-world test environment.