Hardware-Efficient VLSI Architecture and ASIC Implementation of GRCR-Based Cooperative Spectrum Sensor for Cognitive-Radio Network

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 30; no. 2; pp. 166 - 176
• Main Authors: Chaurasiya, Rohit B., Shrestha, Rahul
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.02.2022; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; Application specific integrated circuits; Application-specific integrated circuits (ASICs); Architecture; CMOS; cognitive radio; Computer architecture; Covariance matrices; digital VLSI architectures; Gerschgorin radii and center ratio (GRCR)-based cooperative spectrum sensing (CSS) algorithm; Hardware; Integrated circuits; Optimization; Radio frequency; Radio networks; Sensors; Signal processing; Signal to noise ratio; Very large scale integration; VLSI design; White spaces
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2021.3114859

This article proposes implementation-friendly Gerschgorin radii and center ratio (GRCR)-based cooperative spectrum sensing (CSS) algorithm with reduced computational complexity that delivers adequate performance in uniform- and nonuniform-dynamical noise-and-received signal power scenarios. Subsequently, a new VLSI architecture of cooperative spectrum sensor (CSR) based on the proposed GRCR algorithm and additional architectural optimization has been suggested that consumes lower area and delivers shorter sensing time. Performance analysis of our implementation-friendly GRCR-based CSS algorithm has been carried out under the Rayleigh fading channel, and it delivers adequate area under the receiver-operating-characteristic (ROC) curve (AUC) = 0.9 at an average signal-to-noise ratio (SNR avg ) of −5 dB. Consecutively, an application-specific integrated circuit (ASIC) chip of the proposed CSR has been fabricated in the UMC 130-nm CMOS process. It occupies 0.27 mm 2 of the core area, and its maximum operating frequency is 88.8 MHz at 1.2 V of the supply voltage. At this clock frequency, our CSR delivers a sensing time of <inline-formula> <tex-math notation="LaTeX">5~\mu \text{s} </tex-math></inline-formula> while processing the received signal samples from four secondary users in a cognitive-radio network. These ASIC-implementation results are compared with the reported works in the literature where our design has shown <inline-formula> <tex-math notation="LaTeX">45\times </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">12\times </tex-math></inline-formula> better hardware efficiency and sensing time, respectively, compared to the state-of-the-art implementations.