APA (7th ed.) Citation

Verma, A., & Shrestha, R. (2021). Hardware-Efficient and High-Throughput LLRC Segregation Based Binary QC-LDPC Decoding Algorithm and Architecture. IEEE transactions on circuits and systems. II, Express briefs, 68(8), 2835-2839. https://doi.org/10.1109/TCSII.2021.3071804

Chicago Style (17th ed.) Citation

Verma, Anuj, and Rahul Shrestha. "Hardware-Efficient and High-Throughput LLRC Segregation Based Binary QC-LDPC Decoding Algorithm and Architecture." IEEE Transactions on Circuits and Systems. II, Express Briefs 68, no. 8 (2021): 2835-2839. https://doi.org/10.1109/TCSII.2021.3071804.

MLA (9th ed.) Citation

Verma, Anuj, and Rahul Shrestha. "Hardware-Efficient and High-Throughput LLRC Segregation Based Binary QC-LDPC Decoding Algorithm and Architecture." IEEE Transactions on Circuits and Systems. II, Express Briefs, vol. 68, no. 8, 2021, pp. 2835-2839, https://doi.org/10.1109/TCSII.2021.3071804.