Hardware-Efficient and High-Throughput LLRC Segregation Based Binary QC-LDPC Decoding Algorithm and Architecture

• Published in: IEEE transactions on circuits and systems. II, Express briefs Vol. 68; no. 8; pp. 2835 - 2839
• Main Authors: Verma, Anuj, Shrestha, Rahul
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.08.2021; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; Architecture; Codes; Computer architecture; Decoding; field-programmable gate-array (FPGA); frame error rate (FER); Hardware; Parallel processing; quasi-cyclic low-density-parity-check (QC-LDPC) codes; Routing; Signal to noise ratio; signal-to-noise ratio (SNR); Throughput; Wireless communication
• ISSN: 1549-7747; 1558-3791
• DOI: 10.1109/TCSII.2021.3071804

This brief proposes hardware-friendly QC-LDPC decoding algorithm with layered scheduling based on new logarithmic-likelihood-ratio compound (LLRC) segregation technique. Subsequently, we present hardware-efficient QC-LDPC decoder-architecture based on the proposed algorithm and additional architectural optimizations. This decoder has been designed based on the 5G-NR specifications, supporting code-lengths and code-rates in the ranges of 26112-10368 bits and 1/3-8/9, respectively. Performance analysis has shown that suggested LLRC-segregation based decoding algorithm delivers adequate FER of 10 −5 between 1 to 6.5 dB of SNR range. Furthermore, proposed QC-LDPC decoder is post-route simulated and implemented on the FPGA platform. It operates at a maximum clock frequency of 135 MHz and delivers a peak throughput of 11.02 Gbps. Eventually, comparison with relevant works shows that our decoder delivers <inline-formula> <tex-math notation="LaTeX">2.2\times </tex-math></inline-formula> higher throughput and <inline-formula> <tex-math notation="LaTeX">8.3\times </tex-math></inline-formula> better hardware-efficiency than the state-of-the-art implementations.