High-Performance COTS FPGA SoC for Parallel Hyperspectral Image Compression With CCSDS-123.0-B-1

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 28; no. 11; pp. 2397 - 2409
• Main Authors: Tsigkanos, Antonis, Kranitis, Nektarios, Theodoropoulos, Dimitris, Paschalis, Antonios
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.11.2020; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Airborne sensing; Algorithms; Computer architecture; Consultative Committee for Space Data Systems (CCSDS); Field programmable gate arrays; field-programmable gate array (FPGA); hyperspectral compression; Hyperspectral imaging; Image coding; Image compression; Image segmentation; Launch costs; Object recognition; on-board data processing; Performance evaluation; Remote sensing; Sensors; Small satellites; System on chip; system-on-chip (SoC)
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2020.3020164

Nowadays, hyperspectral imaging is recognized as a cornerstone remote sensing technology. Next generation, high-speed airborne, and space-borne imagers have increased resolution, resulting in an explosive growth in data volume and instrument data rate in the range of gigapixel per second. This competes with limited on-board resources and bandwidth, making hyperspectral image compression a mission critical on-board processing task. At the same time, the "new space" trend is emerging, where launch costs decrease, and agile approaches are exploited building smallsats using commercial-off-the-shelf (COTS) parts. In this contribution, we introduce a high-performance parallel implementation of the CCSDS-123.0-B-1 hyperspectral compression algorithm targeting SRAM field-programmable gate array (FPGA) technology. The architecture exploits image segmentation to provide the robustness to data corruption and enables scalable throughput performance by leveraging segment-level parallelism. Furthermore, we exploit the capabilities of a COTS FPGA system-on-chip (SoC) device to optimize size, weight, power, and cost (SWaP-C). The architecture partitions a hyperspectral cube stored in a DRAM framebuffer into segments, compressing them in parallel using a flexible software scheduler hosted in the SoC CPU and several compressor accelerator cores in the FPGA fabric. A 5-core implementation demonstrated on a Zynq-7045 FPGA achieves a throughput performance of 1387 Msamples/s [22.2 Gb/s at 16 bits per pixel per band (bpppb)] and outperforms previous implementations in equivalent FPGA technology, allowing seamless integration with next-generation hyperspectral sensors.