An Error-Resilient RISC-V Microprocessor With a Fully Integrated DC-DC Voltage Regulator for Near-Threshold Operation in 28-nm CMOS

• Published in: IEEE journal of solid-state circuits Vol. 58; no. 11; pp. 1 - 11
• Main Authors: Wu, Bing-Chen, Chen, Wei-Ting, Liu, Tsung-Te
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.11.2023; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; Calibration; CMOS; Conduction losses; Energy conversion efficiency; Energy efficiency; Error correction; Error detection; Error detection and correction (EDAC); error resilience; fully integrated dc–dc voltage converter; high energy efficiency; microprocessor; Microprocessors; near-threshold voltage (NTV); Random access memory; Regulation; Regulators; Resilience; RISC; RISC-V; Silicon; Static random access memory; sub-threshold voltage; Timing; Voltage control; voltage regulator; Voltage regulators
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2023.3287360

This article presents an energy-efficient microprocessor design that fully integrates an error-resilient RISC-V core and an embedded dc-dc switched-capacitor voltage regulator (SCVR). The proposed design achieves high energy efficiency, high computation performance, and a small system footprint through several innovations. First, in situ error detection and correction (EDAC) flip-flops (FFs) and an error-resilient static random access memory (SRAM) interfacing technique enable error resilience on the microprocessor without any post-silicon calibration requirement. Next, a fully integrated SCVR featuring a multi-rate successive approximation (MRSA) algorithm and a dynamic conduction loss minimization technique is proposed to achieve high conversion efficiency, high-power density, and fast load regulation. A prototype chip that fully integrates the techniques described above was fabricated in the 28-nm standard CMOS technology with an active area of 0.42 mm<inline-formula> <tex-math notation="LaTeX">^{2}</tex-math> </inline-formula>. The measurement results show that the proposed in situ EDAC effectively minimizes the timing margin without any post-silicon calibration to achieve a high-processor performance of 43 MHz with an energy-delay-product (EDP) of 0.57 <inline-formula> <tex-math notation="LaTeX">\text{pJ}\cdot\mu</tex-math> </inline-formula>s, showing the state-of-the-art performance and energy efficiency in the standard CMOS technology.