High-Throughput Rate-Flexible Combinational Decoders for Multi-Kernel Polar Codes

• Published in: IEEE transactions on circuits and systems. I, Regular papers Vol. 70; no. 11; pp. 4492 - 4504
• Main Authors: Rezaei, Hossein, Rajatheva, Nandana, Latva-Aho, Matti
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.11.2023; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; Codes; Complexity theory; Decoders; Decoding; Error-correcting codes; Generators; hardware implementation; Kernel; Kernels; multi-kernel; polar code; Polar codes; polar decoder compiler; Reliability; successivecancellation decoder; Wireless communication systems
• ISSN: 1549-8328; 1558-0806
• DOI: 10.1109/TCSI.2023.3311514

Polar codes have received growing attention in the past decade and have been selected as the coding scheme for the control channel in the fifth generation (5G) wireless communication systems. However, the conventional polar codes have only been constructed by binary (<inline-formula> <tex-math notation="LaTeX">2\times 2 </tex-math></inline-formula>) kernel, which poses block length limitation to powers of 2. To attain more flexible block lengths, multi-kernel polar codes are proposed. In this paper, a combinational architecture for multi-kernel polar codes with high throughput is proposed based on successive cancellation decoding algorithm. The proposed scheme can decode pure-binary, pure-ternary (<inline-formula> <tex-math notation="LaTeX">3\times 3 </tex-math></inline-formula>), and binary-ternary mixed polar codes. The decoder's architecture is rate-flexible, meaning that a new code rate can be assigned to the decoder at every clock cycle. The proposed architecture is validated by FPGA implementation, and the results reveal that a code of size <inline-formula> <tex-math notation="LaTeX">N=81 </tex-math></inline-formula> achieves the coded throughput of 1664.5 Mbps. A Python-based polar compiler is also proposed to automatically generate the HDL modules for target decoders. A designer can input the target block length and kernel ordering of a polar code and get the required VHDL files automatically.