Current-Fed Phase-Shifted Full-Bridge Converter with Secondary Harmonic Current Reduction for Two-Stage Inverter in Energy Storage System

• Published in: IEEE transactions on power electronics Vol. 38; no. 9; pp. 1 - 12
• Main Authors: Huang, Ta-Wei, Chiu, Huang-Jen, Wang, Guan-Chi, Chang, Yu-Chen
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.09.2023; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Batteries; Circuits; Control systems design; Current-fed full bridge; Efficiency; Electric bridges; Electric converters; Energy storage; Impedance method; Inductors; Inverters; Low voltage; MOSFET; Notch filters; phase-shift control; Power generation; second harmonic current; small signal model; soft switching; soft-commutating; Switches; virtual impedance; Voltage control
• ISSN: 0885-8993; 1941-0107
• DOI: 10.1109/TPEL.2023.3282911

For the low voltage, high current, isolated DC-DC converter applications, current-fed type converter has the chance to achieve higher efficiency due to the lower transformer root mean square current compared with other well-known converters such as dual active bridge or LLC. A current-fed phase-shifted full-bridge, CFPSFB converter has the advantages of nearly full range zero-voltage-switching and soft-commutating without large size of passive or active snubber circuit because the phase-shift of secondary full-bridge is controlled to be proportional to the input current. However, as a front-end stage of a single phase inverter, the input secondary harmonic current (SHC) propagating from the output AC load may cause large voltage spike to damage the primary MOSFETs due to losing the soft-commutating property. SHC may also reduce the conversion efficiency and the lifespan of battery intensely. This paper proposes a simple control scheme based on virtual series impedance method with a notch filter in control loop to reduce the SHC and maintain good dynamic performance. A small-signal model of CFPSFB for a reliable controller design is derived and verified by simulation. A 48 V/3 kW maximum output power inverter prototype is built to verify the theoretical analysis. The maximum efficiency of the DC-DC stage is 97.4% and the peak to peak SHC is less than 10% of the average input current.