An SRAM-Based Reconfigurable Cognitive Computation Matrix for Sensor Edge Applications

• Published in: IEEE journal of solid-state circuits Vol. 59; no. 2; pp. 1 - 13
• Main Authors: Peng, Sheng-Yu, Liu, I-Chun, Wu, Yi-Heng, Lin, Ting-Ju, Chen, Chun-Jui, Li, Xiu-Zhu, Cheng, Yong-Qi, Lin, Pin-Han, Hung, Kuo-Hsuan, Tsao, Yu
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.02.2024; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Artificial intelligent circuits; cognitive computation (CC); Computation; computing in memories; computing-in-static random access memory (SRAM); edge computing; Handwriting recognition; Integers; low-power circuits; Mathematical analysis; Matrices (mathematics); Multiplication; Neuromorphics; Power demand; Quadrants; Radial basis function; Random access memory; Reconfiguration; Resultants; Sensors; Static random access memory; Switching circuits; Technological innovation; Voltage
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2023.3303910

A reconfigurable cognitive computation matrix (RCCM) in static random access memory (SRAM) suitable for sensor edge applications is proposed in this article. The proposed RCCM can take multiple analog currents or digital integers as the input vector and perform vector-matrix multiplication with a weight integer matrix. The RCCM can carry out 1-quadrant, 2-quadrant, or 4-quadrant multiplications in the analog domain. Therefore, the digital integers for the inputs or weights stored in the SRAM can be either signed or unsigned, providing extensive usage flexibilities. Furthermore, three commonly used activation functions (AFs), the rectified linear unit (ReLU), radial basis function (RBF), and logistic function are available, converting multiply-accumulation outputs to single-ended currents as the computation results. The resultant output currents can be adopted as the input currents of other RCCMs to facilitate multiple-layer network implementation. A concept-proving prototype chip, including a <inline-formula> <tex-math notation="LaTeX">16\ttimes16</tex-math> </inline-formula> RCCM with 4-bit input and weight resolutions, is designed and fabricated in a 0.18-<inline-formula> <tex-math notation="LaTeX">\um</tex-math> </inline-formula> CMOS process. The computation accuracy that is deteriorated by process variation can be significantly improved by adopting 48 mismatch parameters after calibration. A handwritten digit recognition database, MNIST, is employed to evaluate the chip performance, achieving an average efficiency of <inline-formula> <tex-math notation="LaTeX">3.355~\TOPSperW</tex-math> </inline-formula>.