A Deterministic Low-Complexity Approximate (Multiplier-Less) Technique for DCT Computation

• Published in: IEEE transactions on circuits and systems. I, Regular papers Vol. 66; no. 8; pp. 3001 - 3014
• Main Authors: Huang, Junqi, Nandha Kumar, T., Almurib, Haider A. F., Lombardi, Fabrizio
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.08.2019; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Adders; addition; Approximate DCT; Approximation algorithms; Coefficients; Complexity; Computer simulation; Discrete cosine transform; Discrete cosine transforms; Energy consumption; Field programmable gate arrays; FPGA; Hardware; Image coding; Image compression; low power DCT; Matrix methods; Reconfiguration; Scanning; Video compression; zigzag scanning
• ISSN: 1549-8328; 1558-0806
• DOI: 10.1109/TCSI.2019.2902415

The approximate (multiplier-less) two-dimensional discrete cosine transform (DCT) is a widely adopted technique for image/video compression. This paper proposes a deterministic low-complexity approximate DCT technique that accurately configures the size of the transform matrix (<inline-formula> <tex-math notation="LaTeX">{T} </tex-math></inline-formula>) according to the number of retained coefficients in the zigzag scanning process. This is achieved by establishing the relationship between the number of retained coefficients and the number of rows of the <inline-formula> <tex-math notation="LaTeX">{T} </tex-math></inline-formula> matrix. The proposed technique referred to as the zigzag low-complexity approximate DCT (ZLCADCT), when compared with approximate DCT (ADCT), decreases the number of addition operations and the energy consumption while retaining the PSNR of the compressed image. In addition, the ZLCADCT eliminates the zigzag scanning process used in the ADCT. Moreover, to characterize the deterministic operation of the ZLCADCT, a detailed mathematical model is provided. A hardware platform based on FPGAs is then utilized to experimentally assess and compare the proposed technique; as modular, deterministic, low latency, and scalable, the proposed techniques can be implemented upon any change in the number of retaining coefficients by realizing only a partial reconfiguration of the FPGA resources for the additional required hardware. The extensive simulation and experimental results show the superior performance compared to previous ADCT techniques under different metrics.