Systolic Processor Core for Finite-Field Multiplication and Squaring in Cryptographic Processors of IoT Edge Devices

• Published in: IEEE internet of things journal Vol. 9; no. 2; pp. 1354 - 1360
• Main Author: Ibrahim, Atef
• Format: Journal Article
• Language: English
• Published: Piscataway IEEE 15.01.2022; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; Arithmetic; ASIC; Complexity theory; Cryptography; Delays; Devices; digit-serial systolic processors; Elliptic curve cryptography; embedded security; Energy consumption; green cryptoprocessos; Hardware; Internet of Things; Internet of Things (IoT) edge devices’ security; Microprocessors; modular multiplication and squaring; Multiplication; Multiplication & division; Process control; Reduction; ultralow power devices
• ISSN: 2327-4662; 2327-4662
• DOI: 10.1109/JIOT.2021.3087274

Internet of Things (IoT) edge devices' security is one of the main barriers to use IoT applications on a large scale. Securing these devices is mainly based on using primitive cryptographic algorithms. The hardware implementation of the cryptographic algorithms should be managed to be suitable for these resource-constrained devices. Finite-field arithmetic operations are at the heart of the cryptographic algorithms, and their efficient implementation directly affects the whole performance of the cryptographic algorithm. Filed multiplication operation is the core of the most finite-field arithmetic operations, such as squaring, inversion, and division. Therefore, this article mainly concentrates on efficiently implementing a resource-constrained unified processor core that simultaneously performs multiplication and squaring operations to reduce hardware resources. The offered processor core has a digit-serial systolic structure providing the designer with flexibility to manage the area, delay, and consumed energy to be suitable for IoT edge devices. ASIC results of the developed design and the reported efficient ones indicate that the proposed structure has a meaningful saving in the area and consumed energy for all embedded word-sizes <inline-formula> <tex-math notation="LaTeX">v </tex-math></inline-formula>. The area achieves a reduction varying from 44.7% to 97.46% at <inline-formula> <tex-math notation="LaTeX">v=8 </tex-math></inline-formula>, 35.7% to 95.4% at <inline-formula> <tex-math notation="LaTeX">v=16 </tex-math></inline-formula>, and 57.1% to 95.6% at <inline-formula> <tex-math notation="LaTeX">v=32 </tex-math></inline-formula>. Also, the energy realizes a reduction ranging from 24.0% to 97.7% at <inline-formula> <tex-math notation="LaTeX">v=8 </tex-math></inline-formula>, 7.6% to 97.2% at <inline-formula> <tex-math notation="LaTeX">v=16 </tex-math></inline-formula>, and 25.4% to 98.1% at <inline-formula> <tex-math notation="LaTeX">v=32 </tex-math></inline-formula>. That makes it more suitable for embedded and IoT applications that impose more restrictions on the area and consumed energy.