Scan Chain Architecture with Data Duplication for Multiple Scan Cell Fault Diagnosis

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems Vol. 42; no. 8; p. 1
• Main Authors: Kim, Sunghoon, Jang, Seokjun, Kang, Sungho
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.08.2023; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Circuits; Cost analysis; Design for testability; Diagnostic systems; Fault diagnosis; Faults; flush test; Hardware; hardware-based diagnosis; multiple faults; scan chain diagnosis
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/TCAD.2022.3224899

Scan chain diagnosis is an important step in solving yield problems in early manufacturing processes. The higher the diagnostic resolution, the better the yield in the initial process. In the conventional scan chain architecture, if failed scan chain data are observed during scan mode, all the shifted data through a stuck-at faulty cell are contaminated. As a result, only a single fault can be diagnosed, and there are difficulties in diagnosing multiple stuck-at fault locations. The number of multiple faults has increased significantly, increasing the cost of physical fault analysis. In addition, it is difficult to diagnose faults with a high resolution because there are many candidate faults early in the process. In this paper, a new hardware architecture with data duplication is proposed to diagnose fault locations by deliberate voltage collision even if multiple faults occur. The resources required for the diagnosis include a minimum of one good scan chain, a diagnosis circuit, and a diagnostic line. Experimental results show that the proposed method has lower hardware and routing overhead and fewer additional pin counts than the existing method. The diagnostic speed is also faster, and the larger the number of scan chains (the larger the circuit), the higher the diagnostic performance, which has advantages over conventional methods.