Framework for Automated Earthquake Event Detection Based on Denoising by Adaptive Filter

• Published in: IEEE transactions on circuits and systems. I, Regular papers Vol. 67; no. 9; pp. 3070 - 3083
• Main Authors: Bose, Sudipta, De, Arijit, Chakrabarti, Indrajit
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.09.2020; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Adaptive filters; Adaptive systems; Algorithms; Application specific integrated circuits; Architecture; Automation; Background noise; Computer architecture; Coordinate rotational digital computer (CORDIC); earthquake early warning system (EEWS); Earthquakes; Event detection; Field programmable gate arrays; FPGA and ASIC design; half-unit biased (HUB) format; Integrated circuits; Noise reduction; P waves; Real time; Real-time systems; short-time-average/long-time-average (STA/LTA) algorithm; Signal processing algorithms; Signal to noise ratio; Steady-state; Very large scale integration
• ISSN: 1549-8328; 1558-0806
• DOI: 10.1109/TCSI.2020.2984960

Automated detection of the P-wave arrival for real-time earthquake-early-warning-system employing conventional short-time-average/long-time-average (STA/LTA) algorithm is prone to suffer from erroneous detection due to high background noise. This paper introduces an enhanced variable step-size least mean square (EVSSLMS) algorithm for considerably improving the P-wave detection. The proposed event detection scheme employs the EVSSLMS algorithm for de-noising the seismic data followed by conventional STA/LTA algorithm to detect arrival of the P-wave. The EVSSLMS algorithm outperforms the existing trigonometric least mean square (TLMS), variable step-size LMS (VSSLMS), least mean logarithmic square (LMLS) and variable <inline-formula> <tex-math notation="LaTeX">\alpha </tex-math></inline-formula>-LMLS algorithms in terms of convergence speed and steady-state error and achieves a significant enhancement in detection accuracy by 42%, 33%, 25% and 23% at low signal-to-noise ratio (SNR) as compared to the existing TLMS, VSSLMS, LMLS, and variable-<inline-formula> <tex-math notation="LaTeX">\alpha </tex-math></inline-formula> LMLS algorithms, respectively. Moreover, a high-speed and low-complexity very-large-scale-integrated (VLSI) architecture has been implemented on both field-programmable-gate array (FPGA) and application-specific-integrated circuit (ASIC) platforms for real-time applications. Comparison of architectural performance of the proposed scheme with that of architecture designed to realize variable-<inline-formula> <tex-math notation="LaTeX">\alpha </tex-math></inline-formula> LMLS algorithm exhibits 36% less slice-delay-product whereas, its ASIC implementation exhibits 7.27% less area-delay-product, 9.31% less energy-per-sample with 5.2% more maximum achievable frequency.